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    Dram and its refresh method
    11.
    发明专利
    Dram and its refresh method 审中-公开
    DRAM及其更新方法

    公开(公告)号：JP2003346477A

    公开(公告)日：2003-12-05

    申请号：JP2002153219

    申请日：2002-05-28

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI ,  MORI MASAYA

    IPC: G11C11/406

    CPC classification number: G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

    Abstract: PROBLEM TO BE SOLVED: To provide a DRAM low in power consumption and low in manufacturing cost without needing an SRAM, and to provide a refresh method.
    SOLUTION: This DRAM 10 comprises terminals 18a, 18b to which addresses of memory blocks 16a, 16b, 16c, 16d are inputted, selectors 20a, 20b, 20c, 20d selecting T/C of addresses, and a circuit selecting a block from signal of T or C of an address outputted from the selectors 20a, 20b, 20c, 20d.
    COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：提供功耗低且制造成本低的DRAM而不需要SRAM，并提供刷新方法。 解决方案：该DRAM10包括输入存储块16a，16b，16c，16d的地址的端子18a，18b，选择地址的T / C的选择器20a，20b，20c，20d，以及选择块 从选择器20a，20b，20c，20d输出的地址的T或C信号。 版权所有（C）2004，JPO

    DATA INPUT/OUTPUT METHOD, AND DRAM
    12.
    发明专利
    DATA INPUT/OUTPUT METHOD, AND DRAM 审中-公开

    公开(公告)号：JP2002358783A

    公开(公告)日：2002-12-13

    申请号：JP2001199439

    申请日：2001-06-29

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI

    IPC: G11C11/407 ,  G11C11/409

    Abstract: PROBLEM TO BE SOLVED: To provide a data input/output method which can minimize losses of data interruption at the time of switching between reading and writing in a DRAM using a common input/output section for reading and writing data, and to provide a DRAM. SOLUTION: This data input/output method comprises a step for holding predetermined data from a memory array 12 by a read command of m-th (m is integer), a step for outputting the data to a common input/output section 30 and holding new data from the memory array 12 upon (m+1)-th read command, a step for holding the data from the common input/output section 30 upon n-th (n is integer) write command, and a step for storing the data in the memory array 12 and holding new data from the common input/output section 30 upon (n+1)-th write command.

    Information processor and information processing method, program, data structure and computer readable recording medium
    16.
    发明专利
    Information processor and information processing method, program, data structure and computer readable recording medium 有权
    信息处理器和信息处理方法，程序，数据结构和计算机可读记录介质

    公开(公告)号：JP2004227434A

    公开(公告)日：2004-08-12

    申请号：JP2003016843

    申请日：2003-01-27

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MORI MASAYA ,  WATANABE SHINPEI ,  SUNANAGA TOSHIO ,  TAKATSU YOSHIHISA

    IPC: G06F12/00 ,  G06F7/00 ,  G06F9/26 ,  G06F9/34 ,  G06F17/00 ,  G06F17/30 ,  H04L29/12

    CPC classification number: G06F17/30949 ,  H04L29/12839 ,  H04L61/6022

    Abstract: PROBLEM TO BE SOLVED: To much more efficiently achieve data registration in a data table and data retrieval from the data table.
    SOLUTION: Data registration in a data table (3) in which the first item data are registered with the corresponding second item data and data retrieval from the data table is executed by using a first pointer table (1) in which a pointer to a portion of registered data in the data table is registered at a storage position shown by a hash value obtained by applying a first hash function (6) to the first item data of the registered data and a second pointer table (2) in which the pointer is registered at a storage position shown by a hash value obtained by applying a second hash function (22) to the first item data of the registered data.
    COPYRIGHT: (C)2004,JPO&NCIPI

    Abstract translation: 要解决的问题：更有效地实现数据表中的数据注册和数据表中的数据检索。 解决方案：通过使用第一指针表（1）来执行数据表（3）中数据表（3）中的数据表，其中第一项数据与对应的第二项数据进行登记，并从数据表中进行数据检索，其中指针 将数据表中的登记数据的一部分登记在通过将第一散列函数（6）应用于登记数据的第一项目数据而获得的哈希值所示的存储位置，以及第二指针表（2） 指针被登记在通过将第二散列函数（22）应用于登记数据的第一项目数据而获得的哈希值所示的存储位置。 版权所有（C）2004，JPO＆NCIPI

    DRAM AND METHOD FOR ACCESSING DATA OF DRAM
    18.
    发明专利
    DRAM AND METHOD FOR ACCESSING DATA OF DRAM 失效

    公开(公告)号：JP2000195253A

    公开(公告)日：2000-07-14

    申请号：JP37035898

    申请日：1998-12-25

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO ,  WATANABE SHINPEI

    IPC: G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4091

    Abstract: PROBLEM TO BE SOLVED: To shorten a pre-charging time by providing plural DRAM cells and sense amplifiers respectively in response to plural DRAM cells and activating only the sense amplifier answering to the cell to be accessed among plural DRAM cells. SOLUTION: A DRAM 10 contains a pre-fetch/latch circuit 14, an output buffer 18 connected to the pre-fetch/latch circuit 14 and a pre-load/latch circuit 16 connected to a sense amplifier part 26. Data of 32 pieces of memory cells 20 on a word line 22 are stored in the pre-fetch/latch circuit 14, and the data are read out from the output buffer 18 to four respective outputs. At a writing, the data inputted to plural respective inputs are stored temporarily in the pre- load/latch circuit 16, and when all the 32 pieces of data are inputted, they are written simultaneously in 32 pieces of memory cells 20. The data are pre-loaded to the pre-load/latch circuit 16, and are written back in batch to be automatically pre-charged.

    DATA TRANSFER CONTROLLER
    19.
    发明专利
    DATA TRANSFER CONTROLLER 失效

    公开(公告)号：JPH0765180A

    公开(公告)日：1995-03-10

    申请号：JP19955093

    申请日：1993-08-11

    Applicant: IBM

    Inventor： TAKAYANAGI KAZUNORI ,  WATANABE SHINPEI

    IPC: G06F13/36 ,  G06F13/38 ,  G06T11/00 ,  G09G5/39

    Abstract: PURPOSE: To make a bus transfer protocol programmable and to improve data transferring efficiency by transferring the plural data of a bit value smaller than a prescribed bit width on the bus of the prescribed bit value in one cycle by a programmed operations. CONSTITUTION: This device is provided with a plotting control chip 10, and video chips V1-V4. They are connected through a 64 bit data bus 20, 4 bit program signal line 22, and 1 bit ready signal line 24. Avideo chip V1 is constituted of a decoder DEC1, program buffer address register PBAR, sequencer SEQ, program buffer PB, decoder DEC 2, address control unit 54, selector SEL, and each kind register. The video chip V1 is connected through a data bus 26 with a video buffer APA1.

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