公开(公告)号：DE3476499D1

公开(公告)日：1989-03-02

申请号：DE3476499

申请日：1984-04-12

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WESTCOTT DOUGLAS WAYNE

IPC: H03K3/037

Abstract: A latching circuit with reduced signal delay is disclosed comprising a latch (3') and an output logic function circuit (4'). The same signals are applied to the output gate (1') of the latch and to the logic function circuit (4'), whereby the output gate (1') and the logic function circuit (4') effectively are connected in parallel, rather than in series, to eliminate one level of logic delay. An additional logic signal (f) is applied only to the logic function circuit (4') but not to the latch (3'). Provision can be made for applying inverted data to the latch in the event that the latch and the logic function circuit are implemented with NAND or NOR gates.

公开(公告)号：DE69326573T2

公开(公告)日：2000-04-27

申请号：DE69326573

申请日：1993-01-21

Applicant: IBM

Inventor： BARTOW NEIL GEORGE ,  BROWN PAUL JOSEPH ,  CAPOWSKI ROBERT STANLEY ,  FASANO LOUIS THOMAS ,  GREGG THOMAS ANTHONY ,  SALYER GREGORY ,  SUGRUE PATRICK JOHN ,  WESTCOTT DOUGLAS WAYNE ,  ZEYAK VINCENT PAUL

IPC: H04J3/06 ,  H04L25/02 ,  H04L69/40 ,  H04B1/76 ,  H04L1/16

Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

公开(公告)号：DE69326573D1

公开(公告)日：1999-11-04

申请号：DE69326573

申请日：1993-01-21

Applicant: IBM

Inventor： BARTOW NEIL GEORGE ,  BROWN PAUL JOSEPH ,  CAPOWSKI ROBERT STANLEY ,  FASANO LOUIS THOMAS ,  GREGG THOMAS ANTHONY ,  SALYER GREGORY ,  SUGRUE PATRICK JOHN ,  WESTCOTT DOUGLAS WAYNE ,  ZEYAK VINCENT PAUL

IPC: H04J3/06 ,  H04L25/02 ,  H04L69/40 ,  H04B1/76 ,  H04L1/16

Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

公开(公告)号：DE3380388D1

公开(公告)日：1989-09-14

申请号：DE3380388

申请日：1983-02-28

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WARREN RAYMOND HENRY ,  WESTCOTT DOUGLAS WAYNE

IPC: H03K3/037

Abstract: A hazard-free latch is disclosed comprising three NAND logic gates (1-3), one of the gates (3), in combination with its loading, being relatively fast and another of the gates (2), in combination with its output loading, being relatively slow. Both gates receive an input clock signal. Input data is applied to the third gate (1). The output of the fast gate (3) is connected to another input of the slow gate (2). The outputs of the third (1) and the slow gates (2) are connected to an output terminal and to another input of the fast gate (3).

公开(公告)号：AT28770T

公开(公告)日：1987-08-15

申请号：AT84113733

申请日：1984-11-14

Applicant: IBM

Inventor： MALEY GERALD ADRIAN ,  WESTCOTT DOUGLAS WAYNE

IPC: H03K3/037 ,  H03K5/135

Abstract: An edge triggered polarity hold, clocked latch circuit is disclosed which requires the use of only a single clock line for operation. The latch circuit comprises three set-reset type latches (1, 2, 3). Each of two latches (1, 2) receives one set and one reset signal. The third latch (3) receives two reset signals and one set signal. A single clock signal is applied jointly to a reset terminal of the third latch (3) and of one of the first two latches (1, 2). A data signal is applied to the set terminal of the third latch (3). The other of the first two latches (1,2) constitutes the output latch (2) and is connected to receive the outputs of the remaining latches. The output latch (2) produces an output equal to an input data signal upon each occurrence of the leading edge of an input clock signal. The output is held (latched) until the occurrence of the next clock signal when the output becomes equal to the then existing input data signal.

公开(公告)号：DE3174062D1

公开(公告)日：1986-04-17

申请号：DE3174062

申请日：1981-10-05

Applicant: IBM

Inventor： WESTCOTT DOUGLAS WAYNE

IPC: G11C29/00 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/02 ,  G11C29/20 ,  G11C29/56 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

公开(公告)号：AU522222B2

公开(公告)日：1982-05-20

申请号：AU4428779

申请日：1979-02-15

Applicant: IBM

Inventor： PASCOE ROBERT AUGUST ,  SPROTT CHARLES NORMAN ,  WESTCOTT DOUGLAS WAYNE

IPC: G06F7/78 ,  G06F12/00 ,  G11C19/00 ,  G06F13/00