公开(公告)号：DE69405437D1

公开(公告)日：1997-10-16

申请号：DE69405437

申请日：1994-03-17

Applicant: IBM

Inventor： FUJII YOSHIHARU ,  YOSHIDA TOSHIHIKO

IPC: G02F1/1345

Abstract: A high definition, high quality active matrix type liquid crystal display is provided by excluding electrodes from a single side of two transparent substrates to reduce extra space, whilst also providing transfers in the remaining space. On the side of liquid crystal inlet 14, as on other sides, a plurality of transfers 19 are provided outside seal 24. From transfers 19 on the side of liquid crystal inlet 14, a wiring pattern is formed inwardly, intersecting seal 24, to connect to extended conductor 21 formed in parallel with seal 24. Extended conductor 21 is led toward the side where signal line lead electrode 18 is provided, again crossing seal 24 to be connected with transfer lead electrode 20 formed on that side.

公开(公告)号：DE69405437T2

公开(公告)日：1998-02-26

申请号：DE69405437

申请日：1994-03-17

Applicant: IBM

Inventor： FUJII YOSHIHARU ,  YOSHIDA TOSHIHIKO

IPC: G02F1/1345

Abstract: A high definition, high quality active matrix type liquid crystal display is provided by excluding electrodes from a single side of two transparent substrates to reduce extra space, whilst also providing transfers in the remaining space. On the side of liquid crystal inlet 14, as on other sides, a plurality of transfers 19 are provided outside seal 24. From transfers 19 on the side of liquid crystal inlet 14, a wiring pattern is formed inwardly, intersecting seal 24, to connect to extended conductor 21 formed in parallel with seal 24. Extended conductor 21 is led toward the side where signal line lead electrode 18 is provided, again crossing seal 24 to be connected with transfer lead electrode 20 formed on that side.

公开(公告)号：BR9201561A

公开(公告)日：1993-01-05

申请号：BR9201561

申请日：1992-04-28

Applicant: IBM

Inventor： ATSUMI MASAKAZU ,  MATSUMOTO TAKESHI ,  YOSHIDA TOSHIHIKO

IPC: G02F1/133 ,  G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  G09F9/35

公开(公告)号：DE69407486T2

公开(公告)日：1998-07-02

申请号：DE69407486

申请日：1994-05-24

Applicant: IBM

Inventor： FUJII YOSHIHARU ,  YOSHIDA TOSHIHIKO ,  KITAHARA HIROAKI

IPC: G02F1/133 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/136

Abstract: A liquid crystal display device includes a display region (2) in which a plurality of liquid crystal display elements (10) are formed in a matrix and a peripheral region (3) enclosing the display region (2). The display region (2) includes gate lines (6) arranged in parallel with one another and reference voltage lines (9) each of which is formed between the gate lines (6) and serves as an electrode for a storage capacitor of each of the liquid crystal display elements (10). The peripheral region (3) includes connecting terminals (6) which are separated from each other by distance less than a distance between adjacent gate lines (6) in the display region (2). The connecting terminals (6) are arranged in groups. The gate lines (4) each connected to said connecting terminals (6). A short-circuit line (11) is formed along said peripheral region (3) so that the connecting terminals (6) are short-circuited. A conductor extending from the short-circuit line (11) is formed between a region (7) between the groups and the reference voltage lines (9) which face the region (7). This prevents dielectric breakdown for a storage capacitor of a liquid crystal display element connected to a predetermined gate line in a liquid crystal display device.

公开(公告)号：DE69300154T2

公开(公告)日：1995-12-07

申请号：DE69300154

申请日：1993-06-03

Applicant: IBM

Inventor： YOSHIDA TOSHIHIKO ,  ATSUMI MASAKAZU ,  MATSUMOTO TAKESHI

IPC: G02F1/133 ,  G02F1/136 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: The present invention provides a technique for preventing leak current caused by incident light falling on a semiconductor layer which forms a channel in a thin film transistor (TFT). An insulating layer is formed between said semiconductor layer and at least one of the source and drain electrodes of the TFT, over a distance which is longer than a hole-electron recombination distance from all the edges of at least one of the source and drain electrodes overlapping the semiconductor layer.