公开(公告)号：EP0629895B1

公开(公告)日：1997-12-29

申请号：EP94303692

申请日：1994-05-24

Applicant: IBM

Inventor： FUJII YOSHIHARU ,  YOSHIDA TOSHIHIKO ,  KITAHARA HIROAKI

IPC: G02F1/133 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/136

CPC classification number: G02F1/1345 ,  G02F1/136204

公开(公告)号：DE69407486T2

公开(公告)日：1998-07-02

申请号：DE69407486

申请日：1994-05-24

Applicant: IBM

Inventor： FUJII YOSHIHARU ,  YOSHIDA TOSHIHIKO ,  KITAHARA HIROAKI

IPC: G02F1/133 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/136

Abstract: A liquid crystal display device includes a display region (2) in which a plurality of liquid crystal display elements (10) are formed in a matrix and a peripheral region (3) enclosing the display region (2). The display region (2) includes gate lines (6) arranged in parallel with one another and reference voltage lines (9) each of which is formed between the gate lines (6) and serves as an electrode for a storage capacitor of each of the liquid crystal display elements (10). The peripheral region (3) includes connecting terminals (6) which are separated from each other by distance less than a distance between adjacent gate lines (6) in the display region (2). The connecting terminals (6) are arranged in groups. The gate lines (4) each connected to said connecting terminals (6). A short-circuit line (11) is formed along said peripheral region (3) so that the connecting terminals (6) are short-circuited. A conductor extending from the short-circuit line (11) is formed between a region (7) between the groups and the reference voltage lines (9) which face the region (7). This prevents dielectric breakdown for a storage capacitor of a liquid crystal display element connected to a predetermined gate line in a liquid crystal display device.

公开(公告)号：JPH0713185A

公开(公告)日：1995-01-17

申请号：JP14876293

申请日：1993-06-21

Applicant: IBM

Inventor： KITAHARA HIROAKI ,  FUJII YOSHIHARU ,  YOSHIDA TOSHIHIKO

IPC: G02F1/133 ,  G02F1/1345 ,  G02F1/1362

Abstract: PURPOSE: To prevent dielectric breakdown of the storage capacitor of a liquid crystal display element connected to a specific gate line of a liquid crystal display device. CONSTITUTION: A display area 2 where plural liquid crystal display elements 10 are formed like a matrix and a peripheral area 3 enclosing the display area 2 are included, and the display area 2 includes plural gate lines 4 arranged in parallel with each other and plural reference voltage lines 9 which are formed between gate lines 4 and act as one side electrodes of storage capacitors of liquid crystal display elements 10, and the peripheral area 3 includes plural connection terminals 6 which are separated from each other by a distance L2 shorter than a distance L1 between adjacent gate lines 4 in the display area 2, and connection terminals 6 are divided into plural groups 6A and 6B, and gate lines are connected to connection terminals 6, respectively, and a short-circuit line 11 is formed along the peripheral area 3 so as to short-circuit the connection terminals 6. In this liquid crystal display device, a conductive line 12 extended from the short-circuit line 11 is formed between an area 7 between groups 6A and 6B and the reference voltage line 9 facing the area 7.

公开(公告)号：JP2007163711A

公开(公告)日：2007-06-28

申请号：JP2005358324

申请日：2005-12-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NAKAGAKI YOJI ,  ASAHARA AKIHIRO ,  KIMURA HIDEO ,  KITAHARA HIROAKI ,  NISHIWAKI TATSUYA ,  SHIODA YASUHIKO ,  YAMADA TAKESHI

IPC: G02F1/1337

CPC classification number: G02F1/13378 ,  H01J2237/316

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and a method for forming an alignment layer to make the alignment direction of an alignment layer uniform.
SOLUTION: The apparatus 10 for forming an alignment layer has an ion source 12 generating an ion beam 28 and one or more masks 20 disposed between a substrate 24 and the ion source 12, wherein the mask 20 has a reflective surface 34 in the substrate side. The ion beam 28 is reflected between a thin film 26 being an alignment layer on the substrate and the reflective surface 34 of the mask 20, and the alignment layer is formed by the ion beam with which the thin film 26 is finally irradiated. The alignment direction of the liquid crystal can be made uniform by the shape and layout of the reflective face of the mask. Therefore, a liquid crystal display device with no irregular brightness or colors can be manufactured.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于形成取向层以使取向层的取向方向均匀的装置和方法。 解决方案：用于形成取向层的装置10具有产生离子束28的离子源12和设置在基底24和离子源12之间的一个或多个掩模20，其中掩模20具有反射表面34 基板侧。 离子束28在基板上的取向层的薄膜26和掩模20的反射面34之间反射，取向层由最终照射薄膜26的离子束形成。 可以通过掩模的反射面的形状和布局使液晶的取向方向均匀。 因此，可以制造不具有不规则亮度或颜色的液晶显示装置。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2002050638A

公开(公告)日：2002-02-15

申请号：JP2001162425

申请日：2001-05-30

Applicant: IBM

Inventor： IVAN GEORGE COLGAN ,  KINOSHITA HISANORI ,  KITAHARA HIROAKI ,  KAI R SCHLUEPEN

IPC: G03F1/08 ,  G02F1/1368 ,  G03F7/20 ,  H01L21/027 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method for opening a resist in a region where a semiconductor device is higher. SOLUTION: This method includes a step of forming a conductive layer on a channel-insulating layer for forming a part which is actually higher than a flat periphery region. A photoresist layer is formed on the high part and periphery region, and the amount of exposure to the photoresist on the conductive layer on the high part is reduced by the optical mask of a gray scale, so that the photoresist is left on the upper surface of the high part but will not remain in the periphery region after the development of the photoresist, thus forming a pattern in the photoresist. The conductive layer is etched by following the photoresist, and the electrode of source/drain which is self-aligned to the channel insulating layer is formed.

公开(公告)号：JPH06148688A

公开(公告)日：1994-05-27

申请号：JP1293293

申请日：1993-01-28

Applicant: TOSHIBA CORP ,  IBM

Inventor： OGAWA MEIKO ,  KITAHARA HIROAKI ,  KIMURA SHINICHI ,  ICHIOKA ZENICHI ,  SUZUKI KOHEI

IPC: G02F1/136 ,  G02F1/1335 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/78 ,  H01L29/786 ,  H01L29/784

Abstract: PURPOSE: To prevent the discontinuity defect and the shorting defect of shorting lines and thin film transistors by connecting the shorting line formed along an outer periphery beyond a display area on an insulating substrate within a resistance area constituted of the thin film transistors. CONSTITUTION: Plural address wirings 2 and data wirings 3 are formed on the display area on the insulating substrate 1. The source electrodes 4C of the thin film transistors(TFT) 4 formed at respective crossing points are connected to picture element electrodes 5. The address wirings 2 and the data wirings 3 extend beyond the display area and they are connected to driving pulse input pads 8 and 9 and a resistor 10, TFT 11 and 12 constituting the resistors 10 are connected to the shorting lines 13 which mutually short all the resistors 10. The shorting lines 13 are formed in a ladder form along the outer periphery on the insulating substrate 1. When the address wirings 2 are charged by static electricity, current flows between the shorting lines 13 through the resistors 10 in a direction where the charge is compensated. Thus, voltage generated between the address wirings 2 and the data-wirings 3 can be suppressed.

公开(公告)号：JP2000321600A

公开(公告)日：2000-11-24

申请号：JP13335599

申请日：1999-05-13

Applicant: IBM

Inventor： TAKECHI KAZUTOSHI ,  KITAHARA HIROAKI

IPC: H01L29/786 ,  G02F1/133 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/36

Abstract: PROBLEM TO BE SOLVED: To obtain a high resolution LCD device without increasing the number of data lines and gate lines by forming pixel arraies to which a data signal is impressed via data lines on respective first surfaces of first and second transparent substrates facing each other to reduce effects of point defects and line defects. SOLUTION: Pixel arraies in which a plurality of pixel areas are arranged in the row direction and a column direction and the data signal is impressed to the pixel areas via data lines D are formed on inner surfaces of upper-side and lower-side glass substrates 22, 23, respectively. Then, in each pixel array, plural lines of gate lines G1 to GM are arranged in the row direction, plural lines of data lines D1 to DN are arranged in the column direction and respective plural pieces of pixel areas are formed at intersections of the data lines D and the gate lines G. One pixel area being on the upper side glass substrate 22 and one pixel area which is on the lower-side glass substrate 23 and faces this pixel area form one pixel P of the LCD device.

公开(公告)号：JPH11297668A

公开(公告)日：1999-10-29

申请号：JP6846598

申请日：1998-03-18

Applicant: IBM

Inventor： TAKECHI KAZUTOSHI ,  KITAHARA HIROAKI

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To make it possible to continuously etch a metal layer and then an amorphous silicon layer which is the base layer for the metal layer in one and the same etching equipment, by etching the metal layer selectively against the amorphous silicon layer and then etching the amorphous silicon layer. SOLUTION: A gate insulating film 22 and an amorphous silicon active layer (a-Si:H) 23 are formed on a gate electrode 21 and then a patterned i-stopper layer 24 is formed on the amorphous silicon active layer 23. Nextly, a metal layer 26 including Mo is formed on a substrate 20 formed with an n-type a-Si:H layer 25, and then the metal layer 26 is etched to a specified pattern. At that time, a value of 3 or above can be obtained for the selectivity of Mo against the a-Si:H layer if the flow rate of chlorine gas is 100-500 SCCM, that of oxygen gas is 30-150 SCCM, that of He is 100-500 SCCM, the pressure is 20-400 mTorr, and the high frequency power density is 0.5-1.0 W/cm . After the metal layer 26 is etched, the n-type a-Si:H layer 25 and the a-Si:H layer 23 are etched.

公开(公告)号：JPH10125619A

公开(公告)日：1998-05-15

申请号：JP28769596

申请日：1996-10-09

Applicant: IBM

Inventor： TAKATSUJI HIROSHI ,  TSUJI SATOSHI ,  KITAHARA HIROAKI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To realize a wiring layer of low electric resistance which has superior thermal stability and no defects such as hillock by forming a first layer, whose main component is A and forming a second layer whose main component is amorphous phase having electronic resistance higher than that of the first layer, on the whole surface of the first layer. SOLUTION: A first thin dense layer whose main component is Al is formed on a substrate, and an intermediate layer acting as a conducting layer is formed on the first layer. Via the intermediate layer, a second layer having almost the same composition as the first layer is formed, and a wiring layer is formed. The main phase of the second layer is an amorphous phase having electric resistance higher than the first layer. By adding Cu or the like as an additional element to the wiring layer, an Al-Cu alloy thin film is formed. Thereby a wiring layer of low electric resistance, which has superior thermal stability and stress migration resistance characteristics and is free from defect such as hillock, can be formed.

公开(公告)号：JPH0786230A

公开(公告)日：1995-03-31

申请号：JP19566393

申请日：1993-08-06

Applicant: IBM

Inventor： TSUJIMURA TAKATOSHI ,  KITAHARA HIROAKI

IPC: H01L21/306 ,  C23F1/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/48 ,  H01L29/78 ,  H01L29/786 ,  H01L21/336 ,  H01L29/784

Abstract: PURPOSE: To provide a metal wiring film with improved yield by forming the sectional shape of the metal wiring film in a stable taper with improved controllability and at the same time preventing a worm-eaten defect generated on a wiring. CONSTITUTION: A first metal film 3 that should have a side wall whose sectional shape is in taper shape is formed on a substrate 1, a third metal film 7 with a small diffusion coefficient is formed for both metal films between the first metal film and a second metal film 4 that should be formed as its upper layer film, and further a second metal film 4 is formed as an upper-layer film on the third metal film 7. After that, a resist pattern 5 is formed on the second metal film 4, a first metal film 3 is etched with the patterns of the second metal film 4 and the third metal film 7 and the resist pattern as an etching mask, and the sectional shape of the first metal film 3 is formed in taper shape.