公开(公告)号：CA2149479A1

公开(公告)日：1996-01-29

申请号：CA2149479

申请日：1995-05-16

Applicant: IBM ,  PAILLET GUY

Inventor： PAILLET GUY ,  STEIMLE ANDRE ,  TANNHOF PASCAL

IPC: G06F15/18 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063 ,  G06F15/80

Abstract: There is disclosed the architecture of a neural semiconductor chip first inc luding a neuron unit comprised of a plurality of neuron circuits fed by different buses tran sporting data such as the input vector data, set-up parameters, and control signals. Each neuron circuit includes means for generating local result signals of the "fire" type and a local output signal of the distance or category type on respective buses. An OR circuit p erforms an OR function for all corresponding local result and output signals to generate r espective first global result and output signals on respective buses that are merged in an o n-chip common communication bus shared by all neuron circuits of the chip. An additional O R function is then performed between all corresponding first global result and output sign als to generate second global result and output signals, preferably by dotting on an off-chi p common communication bus in the driver block. This latter bus is shared by all the neural chips that are connected thereon to incorporate a neural network of the desired si ze. In the chip, a multiplexer may select either the first or second global output signal to be reinjected in all neuron circuits of the neural network as a feed-back signal depending on the chip operates in a single or multi-chip environment via a feed-backbus. The feedb ack signal results of a collective processing of all the local signal.

公开(公告)号：FR2957717B1

公开(公告)日：2012-05-04

申请号：FR1052034

申请日：2010-03-22

Applicant: ST MICROELECTRONICS SA ,  IBM

Inventor： JEANNOT SIMON ,  TANNHOF PASCAL

IPC: H01L21/768 ,  H01L21/762 ,  H01L23/535

公开(公告)号：DE60206194T2

公开(公告)日：2006-06-14

申请号：DE60206194

申请日：2002-07-11

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL

IPC: G06N3/00 ,  G06N3/08 ,  G06K9/62 ,  G06N3/063

Abstract: An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.

公开(公告)号：AU2002325379A1

公开(公告)日：2003-02-17

申请号：AU2002325379

申请日：2002-07-11

Applicant: IBM

Inventor： TREMIOLLES GHISLAIN IMBERT DE ,  TANNHOF PASCAL

IPC: G06N3/08 ,  G06K9/62 ,  G06N3/00 ,  G06N3/063

Abstract: An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.

公开(公告)号：DE69430744T2

公开(公告)日：2003-01-30

申请号：DE69430744

申请日：1994-07-28

Applicant: IBM ,  PAILLET GUY

Inventor： STEIMLE ANDRE ,  PAILLET GUY ,  TANNHOF PASCAL

IPC: G06F15/18 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063 ,  G06F15/80

Abstract: There is disclosed the architecture of a neural semiconductor chip (10) first including a neuron unit (11(#)) comprised of a plurality of neuron circuits (11-1, ...) fed by different buses transporting data such as the input vector data, set-up parameters, ... and control signals. Each neuron circuit (11) includes means for generating local result (F, ... ) signals of the "fire" type and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip. An additional OR function is then performed between all corresponding first global result and output signals to generate second global result (R**) and output (OUT**) signals, preferably by dotting on an off-chip common communication bus (COM**-BUS) in the driver block (19). This latter bus is shared by all the neural chips that are connected thereon to incorporate a neural network of the desired size. In the chip, a multiplexer (21) may select either the first or second global output signal to be reinjected in all neuron circuits of the neural network as a feed-back signal depending on the chip operates in a single or multi-chip environment via a feed-back bus (OR-BUS). The feedback signal results of a collective processing of all the local signal.

公开(公告)号：CA2149478A1

公开(公告)日：1996-01-29

申请号：CA2149478

申请日：1995-05-16

Applicant: IBM ,  PAILLET GUY

Inventor： BOULET JEAN YVES ,  LOUIS DIDIER ,  GODEFROY CATHERINE ,  PAILLET GUY ,  STEIMLE ANDRE ,  TANNHOF PASCAL

IPC: G06F15/18 ,  G06K9/66 ,  G06N3/00 ,  G06N3/06 ,  G06N3/063 ,  G06N3/08 ,  G06F15/80

Abstract: In a neural network comprised of a plurality of neuron circuits, there is disclosed an improved neuron circuit architecture (11) that generates local result signals, e.g. of the fire (F) type and a local output signal of the distance or category type. The neuron circuit which is connected to buses which transport input data (e.g. the input category) and control signals includes the following circuits. A multi-norm distance evaluation circuit (300) calculates the distance D between the input vector (A) and the prototype vector (B) stored in a R/W (weight) memory circuit (250). A distance compare circuit (300) compares the distance D with either the actual influence field (AIF) of the stored prototype vector or the lower limit thereof (MinIF) to generate first and secondintermediate signals (LT, LTE). An identification circuit (400) processes the said intermediate result signals, the input category signal (CAT), the local category signal (C) and a feedback signal (OR) to generate the local result signals which represent the response of a neuron circuit to the presentation of an input vector. A minimum distance determination circuit (500) is adapted to determine the minimum distance Dmin among all the distances calculated by all the neuron circuits of the neural network to generate a local output signal (NOUT) of the distance type. The same processing applies to categories . The feed-back signal which is collectively generated by all the neuron circuits results of ORing all the local distances/categories. A daisy chain circuit (600) is serially connected to the corresponding daisy chain circuits of the two adjacent neuron circuits to structure the neural network as a chain. Its role is to determine the neuron circuit state: free (in particular, the first free in the chain) and engaged. Finally, a context circuitry (100/150) is capable to allow or not the neuron circuit to participate with the other neuron circuits in the generation of the said feedback signal.

公开(公告)号：DE60234900D1

公开(公告)日：2010-02-11

申请号：DE60234900

申请日：2002-11-13

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL

IPC: G06T3/40

Abstract: An artificial neural network (ANN) based system that is adapted to process an input pattern to generate an output pattern related thereto having a different number of components than the input pattern. The system (26) is comprised of an ANN (27) and a memory (28), such as a DRAM memory, that are serially connected. The input pattern (23) is applied to a processor (22), where it can be processed or not (the most general case), before it is applied to the ANN and stored therein as a prototype (if learned). A category is associated with each stored prototype. The processor computes the coefficients that allow the determination of the estimated values of the output pattern, these coefficients are the components of a so-called intermediate pattern (24). Assuming the ANN has already learned a number of input patterns, when a new input pattern is presented to the ANN in the recognition phase, the category of the closest prototype is output therefrom and is used as a pointer to the memory. In turn, the memory outputs the corresponding intermediate pattern. The input pattern and the intermediate pattern are applied to the processor to construct the output pattern (25) using the coefficients. Typically, the input pattern is a block of pixels in the field of scaling images.

公开(公告)号：AT453903T

公开(公告)日：2010-01-15

申请号：AT02368124

申请日：2002-11-13

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL

IPC: G06T3/40

Abstract: An artificial neural network (ANN) based system that is adapted to process an input pattern to generate an output pattern related thereto having a different number of components than the input pattern. The system (26) is comprised of an ANN (27) and a memory (28), such as a DRAM memory, that are serially connected. The input pattern (23) is applied to a processor (22), where it can be processed or not (the most general case), before it is applied to the ANN and stored therein as a prototype (if learned). A category is associated with each stored prototype. The processor computes the coefficients that allow the determination of the estimated values of the output pattern, these coefficients are the components of a so-called intermediate pattern (24). Assuming the ANN has already learned a number of input patterns, when a new input pattern is presented to the ANN in the recognition phase, the category of the closest prototype is output therefrom and is used as a pointer to the memory. In turn, the memory outputs the corresponding intermediate pattern. The input pattern and the intermediate pattern are applied to the processor to construct the output pattern (25) using the coefficients. Typically, the input pattern is a block of pixels in the field of scaling images.

公开(公告)号：AT364866T

公开(公告)日：2007-07-15

申请号：AT00480106

申请日：2000-11-14

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL ,  LOUIS DIDIER

IPC: G06F7/02 ,  G06F7/22 ,  G06F7/544

Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=Kxn). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a "thermometric" coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.

公开(公告)号：DE60206194D1

公开(公告)日：2005-10-20

申请号：DE60206194

申请日：2002-07-11

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL

IPC: G06N3/08 ,  G06K9/62 ,  G06N3/00 ,  G06N3/063

Abstract: An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.