公开(公告)号：WO03012737A2

公开(公告)日：2003-02-13

申请号：PCT/EP0208473

申请日：2002-07-11

Applicant: IBM ,  IBM FRANCE

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL

IPC: G06N3/08 ,  G06K9/62 ,  G06N3/00 ,  G06N3/063

CPC classification number: G06K9/6276 ,  G06N3/063

Abstract: There is disclosed an improved artificial neural network (ANN) (120') comprised of a conventional ANN (120), a database block (220) and a compare & update circuit (230). The conventional ANN is formed by a plurality of n neurons (130), each neuron having a prototype memory (140) dedicated to store a prototype and a distance evaluator (150) to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The data base block is comprised of three data bases: a first data base (222) containing all the p prototypes arranged in s slices, each slice being capable to store up to n prototypes, a second data base (224) being capable to store the q input patterns to be presented to the ANN (queries) and a third data base (226) being capable to store the q distances resulting of said evaluation performed during the recognition/classification phase. The role of the compare & update circuit is to compare said distance with the distance previously found for the same input pattern (or pre-existing at initialization) and based upon the result of that comparison, to update or not said distance previously stored.

Abstract translation: 公开了一种由常规ANN（120），数据库块（220）和比较和更新电路（230）组成的改进的人造神经网络（ANN）（120'）。 常规ANN由多个n个神经元（130）形成，每个神经元具有专用于存储原型的原型存储器（140）和距离评估器（150），以评估呈现给ANN的输入模式与 原型存储在其中。 数据库块由三个数据库组成：第一数据库（222），包含以s个片段排列的所有p个原型，每个片段能够存储多达n个原型，第二数据库（224）能够存储 要呈现给ANN（查询）的q个输入模式和第三数据库（226）能够存储在识别/分类阶段期间进行的所述评估的结果。 比较和更新电路的作用是将所述距离与先前针对相同输入模式找到的距离进行比较（或者在初始化时预先存在），并且基于该比较的结果来更新或不更新先前存储的所述距离。

公开(公告)号：JP2003044829A

公开(公告)日：2003-02-14

申请号：JP2001207893

申请日：2001-07-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： DE TREMIOLLES GHISLAIN IMBERT ,  TANNHOF PASCAL

IPC: G06N3/06 ,  G06N3/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for relating a norm with each component of an input pattern presented in an artificial neural network(ANN) based on an input space mapping algorithm during a distance evaluation processing.
SOLUTION: A set of norms called a 'component' norm is stored in a special storing means in the ANN. The ANN is provided with a global memory for storing the whole component norms that are common to the whole neurons in the ANN. The whole neurons use a corresponding prototype component stored in the global memory in each input pattern component and use a related prototype norm to carry out a basic (or partial) distance calculation during distance evaluation processing. Then, a 'distance' norm is used to combine distance basic calculations, and the final distance between the input pattern and a prototype stored in a neuron is determined.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种方法和电路，用于在距离评估处理期间基于输入空间映射算法，将范数与在人造神经网络（ANN）中呈现的输入模式的每个分量相关联。 解决方案：将一组称为“分量”范数的规范存储在ANN中的特殊存储装置中。 ANN具有全局存储器，用于存储ANN中整个神经元共有的整个分量规范。 整个神经元使用存储在每个输入模式组件中的全局存储器中的对应的原型分量，并使用相关的原型范数在距离评估处理期间执行基本（或部分）距离计算。 然后，使用“距离”范数来组合距离基本计算，并且确定输入模式和存储在神经元中的原型之间的最终距离。

公开(公告)号：JP2001236207A

公开(公告)日：2001-08-31

申请号：JP2000387095

申请日：2000-12-20

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  LOUIS DIDIER ,  TANNHOF PASCAL

IPC: G06F7/02 ,  G06F7/22

Abstract: PROBLEM TO BE SOLVED: To retrieves the minimum/maximum values in the group of numbers. SOLUTION: At first, p numbers encoded on q bits are turned into K (q>=K×n) partial values encoded on n bits, and parameters k (k=1-K) for respectively assigning ranks to the partial value of each number are defined so that K bit slices can be formed, and each slice is constituted of the plural partial values having the same rank. Then, each partial value is encoded on m bits (m>n) by using a 'thermometric' encoding technique. Afterwards, the minimum partial value in the first slice (MSB) of the encoded partial values is decided by a parallel type retrieval, and all the numbers related with the larger partial values than the partial value are selectively released. An evaluation process is repeated in the same configuration until the last slice (LSB) is processed, and the number selected as it is in the final stage is allowed to have the minimum value.

公开(公告)号：CA2351040A1

公开(公告)日：2002-01-13

申请号：CA2351040

申请日：2001-06-19

Applicant: IBM

Inventor： TANNHOF PASCAL ,  IMBERT DE TREMIOLLES GHISLAIN

IPC: G06N3/06 ,  G06K9/62 ,  G06N3/063 ,  G06N3/02

Abstract: The method and circuits of the present invention aim to associate a norm to each component of an input pattern presented to an input space mapping algorithm based artificial neural network (ANN) during the distance evaluation process. The set of norm s, referred to as the "component" norms is memorized in specific memorization means in the ANN . In a first embodiment, the ANN is provided with a global memory, common for all the neurons of the ANN, that memorizes all the component norms. For each component of the input pattern, all the neurons perform the elementary (or partial) distance calculation with the corresponding prototype components stored therein during the distance evaluation process using the associated component norm. The distance elementary calculations are then combined using a "distance" norm to determine the final distance between the input pattern and the prototypes stored in the neurons. In another embodiment, the set of component norms is memorized in t he neurons themselves in the prototype memorization means, so that the global memory is no longer physically necessary. This implementation allows to significantly optimize t he consumed silicon area when the ANN is integrated in a silicon chip.

公开(公告)号：DE68924426T2

公开(公告)日：1996-05-02

申请号：DE68924426

申请日：1989-10-26

Applicant: IBM

Inventor： MOLLIER PIERRE ,  NUEZ JEAN-PAUL ,  TANNHOF PASCAL

IPC: H03K19/013 ,  H03K19/086

Abstract: The base circuit (30) comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages (VEE1, VC) and a push-pull output buffer stage (32) connected between second and third supply voltages (VC, VEE2). The push-pull output buffer stage (32) comprises a pull-up transistor (TUP) and a pull-down transistor (TDN) connected in series with the circuit output node (OUT3) coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by said preamplifier. Both branches of the preamplifier are tied at a first output node (M). A current source (I) is connected to said first output node. The first branch comprises a logic block (LB) performing the desired logic function of the base circuit that is connected through a load resistor (R1) to said second supply voltage (VC). In this instance, logic block consists of three parallel-connected input NPN transistors (T1, T2, T3), whose emitters are coupled together at said first output node (M) for NOR operation. The second branch is comprised of a biasing/coupling block (BB) connected to said second supply voltage and coupled both to said first output node (M) and to base node (B) of said pull-down transistor. In a preferred embodiment, this block consists of a diode-connected transistor (TC) and of a resistor (RC) connected in series with the base node (B) coupled therebetween. This block ensures both the appropriate polarization of said nodes (M, B) in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal (S) from node M to node B in AC, when input transistors of the logic block (LB) are ON. Optionally, the AC transmission can be improved by mounting a capacitor (C) between said first output and base nodes. An antisaturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.

公开(公告)号：FR2957717A1

公开(公告)日：2011-09-23

申请号：FR1052034

申请日：2010-03-22

Applicant: ST MICROELECTRONICS SA ,  IBM

Inventor： JEANNOT SIMON ,  TANNHOF PASCAL

IPC: H01L21/768 ,  H01L21/762 ,  H01L23/535

Abstract: L'invention concerne un procédé de formation d'une structure capacitive (C) dans un niveau métallique (Mn) d'un empilement d'interconnexion comprenant une succession de niveaux métalliques et de niveaux de vias, comprenant les étapes suivantes : (a) former, dans ledit niveau métallique, au moins une piste conductrice (34) dans laquelle est définie une tranchée ; (b) former, de façon conforme, une couche isolante (54) sur la structure ; (c) former, dans la tranchée, un matériau conducteur (58) ; et (d) réaliser une planarisation de la structure.

公开(公告)号：DE3854155T2

公开(公告)日：1996-02-29

申请号：DE3854155

申请日：1988-04-29

Applicant: IBM

Inventor： MOLLIER PIERRE ,  TANNHOF PASCAL

IPC: H01L27/095 ,  H03K5/02 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0952

Abstract: The present invention relates in general to fast logic circuits, and more particularly to a family of new GaAs MESFET logic circuits including push pull output buffers, which exhibits very strong output driving capability and very low power consumption at fast switching speeds. A typical 3 Way OR/NOR circuit includes a standard differential amplifier (DA), the first branch of which is controlled by logic input signals (E1, E3, E3). The second branch includes a current switch (T12) controlled by a reference voltage (VREF). The differential amplifier provides first and second output signals (S1, S2), simultaneous and complementary each other. The circuit further includes two push pull output buffers (PP21, PP22). First output buffer (PP21) comprises an active pull up device (FET T13) connected in series with an active pull down device (FET T20), the first circuit output signal (A1) is available at their common node or at the output terminal (21). The active pull up device (T13) is controlled by a first output signal (S1) of the differential amplifier, the active pull down device (T20) is preferably controlled by the second output signal (S2) through an intermediate source follower buffer (IB22). The second output buffer (PP22) is of similar structure, in order to supply the complementary second circuit output signal (B1). The circuit takes advantage of the fact that output signals (S1, S2) are available simultaneously and complementary each other on the outputs of the differential amplifier at output nodes (13, 14) to perform the logic function. The depicted circuit is of the dual phase type because it provides complementary circuit output signals (A1, B1). However, if only one phase of the circuit output signal (e.g. A1) is needed, the number of required devices can be reduced in the output circuit block (16). The output buffer (PP22) and the intermediate buffer (IB21) which cooperate to supply the opposite phase (B1) can be eliminated. The number of devices can be even further reduced by eliminating the other remaining intermediate buffer (IB22). The gate electrode of the active pull down device (T20) is directly controlled by the second output signal (S2) complementary to the first output signal (S1) which controls the corresponding active pull up device (T13).

公开(公告)号：FR2957717B1

公开(公告)日：2012-05-04

申请号：FR1052034

申请日：2010-03-22

Applicant: ST MICROELECTRONICS SA ,  IBM

Inventor： JEANNOT SIMON ,  TANNHOF PASCAL

IPC: H01L21/768 ,  H01L21/762 ,  H01L23/535

公开(公告)号：DE60206194T2

公开(公告)日：2006-06-14

申请号：DE60206194

申请日：2002-07-11

Applicant: IBM

Inventor： IMBERT DE TREMIOLLES GHISLAIN ,  TANNHOF PASCAL

IPC: G06N3/00 ,  G06N3/08 ,  G06K9/62 ,  G06N3/063

Abstract: An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.

公开(公告)号：AU2002325379A1

公开(公告)日：2003-02-17

申请号：AU2002325379

申请日：2002-07-11

Applicant: IBM

Inventor： TREMIOLLES GHISLAIN IMBERT DE ,  TANNHOF PASCAL

IPC: G06N3/08 ,  G06K9/62 ,  G06N3/00 ,  G06N3/063

Abstract: An improved Artificial Neural Network (ANN) is disclosed that comprises a conventional ANN, a database block, and a compare and update circuit. The conventional ANN is formed by a plurality of neurons, each neuron having a prototype memory dedicated to store a prototype and a distance evaluator to evaluate the distance between the input pattern presented to the ANN and the prototype stored therein. The database block has: all the prototypes arranged in slices, each slice being capable to store up to a maximum number of prototypes; the input patterns or queries to be presented to the ANN; and the distances resulting of the evaluation performed during the recognition/classification phase. The compare and update circuit compares the distance with the distance previously found for the same input pattern updates or not the distance previously stored.