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29 records (took 0.026 seconds)

    13.
    发明专利
    未知

    公开(公告)号：ES2160770T3

    公开(公告)日：2001-11-16

    申请号：ES96304352

    申请日：1996-06-10

    Applicant: IBM

    Inventor： HASSNER MARTIN AURELIANO ,  TAMURA TETSUYA ,  WINOGRAD SHMUEL

    IPC: G11B20/10 ,  G11B20/14 ,  G11B20/18

    Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.

    14.
    发明专利
    未知

    公开(公告)号：DE69424229D1

    公开(公告)日：2000-06-08

    申请号：DE69424229

    申请日：1994-06-27

    Applicant: IBM

    Inventor： HASSNER MARTIN AURELIANO ,  KARNIN EHUD DOV ,  SCHWIEGELSHOHN UWE ,  TAMURA TETSUYA

    IPC: G06F5/00 ,  G06T9/00 ,  H03M7/30 ,  H04B1/66 ,  G06F7/02

    Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.

    Maximum -likelihood symbol detection for RLL-coded data
    15.
    发明专利
    Maximum -likelihood symbol detection for RLL-coded data 未知

    公开(公告)号：SG42404A1

    公开(公告)日：1997-08-15

    申请号：SG1996009788

    申请日：1996-05-13

    Applicant: IBM

    Inventor： HASSNER MARTIN AURELIANO ,  TAMURA TETSUYA ,  WINOGRADE SHMUEL

    IPC: G11B20/10 ,  G11B20/14 ,  G11B20/18 ,  H03M7/00

    Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.

    16.
    发明专利
    未知

    公开(公告)号：BR9402666A

    公开(公告)日：1995-05-02

    申请号：BR9402666

    申请日：1994-07-08

    Applicant: IBM

    Inventor： HASSNER MARTIN AURELIANO ,  KARNIN EHUD DOV ,  SCHWIEGELSHOHN UWE ,  TAMURA TETSUYA

    IPC: G06F5/00 ,  G06T9/00 ,  H03M7/30 ,  H04B1/66 ,  H03M7/50 ,  G06F9/28

    Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.

    17.
    发明专利
    未知

    公开(公告)号：DE68921855D1

    公开(公告)日：1995-04-27

    申请号：DE68921855

    申请日：1989-11-10

    Applicant: IBM

    Inventor： ABDEL-GHAFFAR KHALED ,  HASSNER MARTIN AURELIANO

    IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  H03M13/29

    Abstract: A method and means is described for correcting multiple error bursts in data recorded on a storage medium in blocks, comprising a plurality of sub-blocks. After reading the data, decoded block check syndromes are algebraically summed with estimated block check syndromes to provide a set of syndromes for a code for locating sub-blocks having an error burst. This set of syndromes is decoded to identify each sub-block having an error burst. Concurrently block level syndromes are computed to identify the locations and values of errors within the sub-blocks having error bursts. During writing, the data in all sub-blocks of a block is encoded and block level syndromes are generated for these sub-blocks. These block level syndromes are multiplied by a series of preselected weighting factors ( alpha ... alpha ) according to the location index l of the sub-block within the block and as multiplied, each is stored in a different one of B buffers. These are cumulatively summed to produce block check syndromes, which are encoded after the last sub-block of the block is written to provide check bytes for their protection. These check bytes and the weighted cumulative sums are stored on the medium at the end of the block as block check syndromes. , and more specifically relates to such a method and means which includes error correction code (ECC) for which decoded and estimated block check syndromes are generated

    19.
    发明专利
    未知

    公开(公告)号：AT230891T

    公开(公告)日：2003-01-15

    申请号：AT99928152

    申请日：1999-07-01

    Applicant: IBM

    Inventor： HASSNER MARTIN AURELIANO ,  HEISE NYLES ,  HIRT WALTER ,  TRAGER BARRY MARSHALL

    IPC: G11B20/14 ,  G11B20/10 ,  H03M5/14 ,  H03M7/00 ,  H03M7/14 ,  H03M13/00

    Abstract: A method and means for reducing high-duty-cycle unconstrained binary signal sequences in storage and communications processes and systems by invertibly mapping such sequences into a (1, k) rate ⅔ RLL codestream constrained to a duty cycle substantially approximating one-third. That is, binary sequences ordinarily mapping into high-duty-cycle RLL-code sequences are either inhibited from repeating indefinitely or excluded.

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