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公开(公告)号：DE10257142A1
公开(公告)日：2004-06-24
申请号：DE10257142
申请日：2002-12-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD
Abstract: The circuit has a first branch with a series circuit comprising a resistor (R4) which drops a first reference voltage, a first current source (P1) and a parallel circuit comprising at least one second resistor (R1) and a pn-junction (T1). A second branch of the circuit includes a series circuit comprising a third resistor (R5) which drops a second reference voltage, a second current source, and a parallel circuit comprising at least one fourth resistor (R2) and at least one pn-junction (T2). The branches are connected between VDD and VSS. The current densities in the pn-junctions are different.
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公开(公告)号：AU3723201A
公开(公告)日：2001-08-14
申请号：AU3723201
申请日：2001-01-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD
Abstract: A folding stage of the convertor has means for sensitizing, inhibiting and enabling signal paths through the convertor such that in a first operating condition, first and second inputs to the stage are switched through to corresponding inputs of a differential amplifier (3) of the respective stage. In a second operating condition a low auxiliary potential is applied to the first input and a high auxiliary potential is applied to the second input. In a third condition a high auxiliary potential is applied to the first input and a low auxiliary potential is applied to the second input. In a fourth condition both inputs are set to a potential between the high and low potentials. Means (13) are also provided to set the amplifier outputs to the same potential in dependence on signals on a control bus (18). Means are also provided feed a signal from a comparator or differential amplifier via an interrogation bus (19) to a control unit (20). Independent claims also cover a self calibration method.
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公开(公告)号：DE10164966B4
公开(公告)日：2010-04-29
申请号：DE10164966
申请日：2001-11-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD , GREGORIUS PETER
Abstract: The arrangement has a commutator (1) for oversampling the received signal (S) so that several sample values of a bit cell transmitted with the signal are distributed successively to several output ports and output as intermediate signals, two stages (5,6) for combining first and second groups of intermediate signals to form data and clock recovery signals and a phase regulator (7,8) for setting sampling phases for oversampling the received signal.
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公开(公告)号：DE10203596C1
公开(公告)日：2003-08-14
申请号：DE10203596
申请日：2002-01-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD , GREGORIUS PETER
Abstract: Method for sampling phase control for clock and data recovery of a data signal includes sampling a received data signal with a first sampling signal comprising equidistant sampling pulses, minimizing phase deviation between the first sampling signal and the phase of the received data signal to generate an adjusted second sampling signal, and sampling the received data signal with the adjusted second sampling signal to generate sampling data values. The method also includes integrating the sampling data values of the sampled data signal to form a summation value, and altering the phase of sampling pulses of the adjusted second sampling signal until the integrated summation value exceeds a threshold value that can be set.
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公开(公告)号：DE10134450A1
公开(公告)日：2003-02-06
申请号：DE10134450
申请日：2001-07-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD
Abstract: A comparator generates an output signal for controlling switches (S1,S2) connected, so as to control driving state of the transistor (T1). The potential to be applied to the input terminal (KB) in the current-controlled mode differs from that in the voltage-controlled mode and from a potential at the input terminal (KA) in the current-controlled mode.
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Patent Agency Ranking
公开(公告)号：DE10007408A1
公开(公告)日：2001-09-06
申请号：DE10007408
申请日：2000-02-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： MENKHOFF ANDREAS , ENGL BERNHARD
Abstract: An analog-to-digital (A/D) converter circuit arrangement includes an A/D converter (1) and a control device (2-4) for calibrating the A/D converter (1), the control device (2-4) being designed so that it supplies a pre-defined analog input signal value for calibrating the A/D converter (1), evaluates/analyses through this the adapting behaviour of the A/D converter (1) and depending on this, has an effect on the A/D converter (1). The control device (2-4) is designed so that it supplies a pre- defined input signal value for calibrating the converter (1) and evaluates or analyses the digital output signal value of the converter (1) resulting from this.
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公开(公告)号：DE50115073D1
公开(公告)日：2009-10-08
申请号：DE50115073
申请日：2001-01-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD
Abstract: A folding stage of the convertor has means for sensitizing, inhibiting and enabling signal paths through the convertor such that in a first operating condition, first and second inputs to the stage are switched through to corresponding inputs of a differential amplifier (3) of the respective stage. In a second operating condition a low auxiliary potential is applied to the first input and a high auxiliary potential is applied to the second input. In a third condition a high auxiliary potential is applied to the first input and a low auxiliary potential is applied to the second input. In a fourth condition both inputs are set to a potential between the high and low potentials. Means (13) are also provided to set the amplifier outputs to the same potential in dependence on signals on a control bus (18). Means are also provided feed a signal from a comparator or differential amplifier via an interrogation bus (19) to a control unit (20). Independent claims also cover a self calibration method.
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公开(公告)号：DE50113617D1
公开(公告)日：2008-04-03
申请号：DE50113617
申请日：2001-06-12
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD
IPC: H03F1/08
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公开(公告)号：DE10157437B4
公开(公告)日：2007-04-26
申请号：DE10157437
申请日：2001-11-23
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD , GREGORIUS PETER
Abstract: The arrangement has a commutator (1) for oversampling the received signal (S) so that several sample values of a bit cell transmitted with the signal are distributed successively to several output ports and output as intermediate signals, two stages (5,6) for combining first and second groups of intermediate signals to form data and clock recovery signals and a phase regulator (7,8) for setting sampling phases for oversampling the received signal.
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公开(公告)号：DE10042584B4
公开(公告)日：2004-02-05
申请号：DE10042584
申请日：2000-08-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ENGL BERNHARD
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