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    12.
    发明专利
    未知

    公开(公告)号：DE59607510D1

    公开(公告)日：2001-09-20

    申请号：DE59607510

    申请日：1996-09-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KERBER MARTIN

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/788 ,  H01L29/792

    Abstract: The field insulation in a flash memory cell is provided by an oxide/polysilicon/oxide sandwich. The memory cell area is reduced by dopant implantation, self-aligned with respect to the word lines of two adjacent memory cells, for producing the source regions and source connections. The field insulation produces a capacitance between the doping region and the polysilicon layer of the insulation layer which improves the read characteristic of the memory cell.

    13.
    发明专利
    未知

    公开(公告)号：DE10344388A1

    公开(公告)日：2005-05-19

    申请号：DE10344388

    申请日：2003-09-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KERBER MARTIN ,  HATZOPOULOS NIKOLAOS

    IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/316 ,  H01L29/51 ,  H01L21/336 ,  H01L21/31

    Abstract: A method eliminates effects of defects on wafers caused by cavities adjacent to the surface of a semiconductor (e.g., silicon) wafer. A first insulating layer is applied to the surface of the semiconductor wafer and into the cavities adjacent to the surface. The applied first insulating layer is covered with a sacrificial layer. A selective back-etching of the sacrificial layer is carried out, such that the cavities adjacent to the surface remain filled with the sacrificial layer. A second insulating layer is applied directly to the first insulating layer and, in a subsequent method step, a conducting layer is applied to the second insulating layer.

    14.
    发明专利
    未知

    公开(公告)号：AT204404T

    公开(公告)日：2001-09-15

    申请号：AT96938008

    申请日：1996-09-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KERBER MARTIN

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/788 ,  H01L29/792

    Abstract: The field insulation in a flash memory cell is provided by an oxide/polysilicon/oxide sandwich. The memory cell area is reduced by dopant implantation, self-aligned with respect to the word lines of two adjacent memory cells, for producing the source regions and source connections. The field insulation produces a capacitance between the doping region and the polysilicon layer of the insulation layer which improves the read characteristic of the memory cell.

    Production of integrated semiconductor circuit comprises deforming and/or making smaller mask islands before applying sink dopants to produce low ohmic contacts
    15.
    发明专利
    Production of integrated semiconductor circuit comprises deforming and/or making smaller mask islands before applying sink dopants to produce low ohmic contacts 未知

    公开(公告)号：DE19944303A1

    公开(公告)日：2001-04-19

    申请号：DE19944303

    申请日：1999-09-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KERBER MARTIN

    IPC: H01L21/285 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/266 ,  H01L21/283

    Abstract: The mask islands (1, 2) are deformed and/or made smaller before applying the sink dopants (7, 8) to produce low ohmic contacts so that the sink dopants penetrate the mask islands and are applied closer to the substrate surface than outside the islands. Production of an integrated semiconductor circuit comprises preparing a substrate with a surface having contact openings; applying and structuring a first mask foil in such a way that mask islands (1) remain on first contact openings (A) and mask holes (3) are produced on second contact openings (B); applying a dopant of a first conducting type (5) close to the surface and a sink dopant of a second type (7); applying and structuring a second mask film in such a way that mask islands (2) remain on the second contact openings and mask holes are produced on the first contact openings; and applying a dopant of second conducting type (6) close to the surface and a sink dopant of first conducting type (8). The mask islands (1, 2) are deformed and/or made smaller before applying the sink dopants (7, 8) to produce low ohmic contacts so that the sink dopants penetrate the mask islands and are applied closer to the substrate surface than outside the islands. Preferred Features: The contact openings (A) are connected to p(n)-MOS transistors and the contact openings (B) are connected to n(p)-MOS transistors.

    Halbleiterstruktur samt Schutzring
    16.
    发明专利
    Halbleiterstruktur samt Schutzring 未知

    公开(公告)号：DE102012109164B4

    公开(公告)日：2019-10-02

    申请号：DE102012109164

    申请日：2012-09-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KERBER MARTIN ,  STECHER MATTHIAS

    IPC: H01L23/528 ,  H01F27/28 ,  H01L21/768

    Abstract: Halbleiterstruktur (1012), aufweisend:ein leitfähiges Merkmal (MF2);einen äußeren Schutzring (GR1); undeinen inneren Schutzring (GR2) zwischen dem äußeren Schutzring (GR1) und dem leitfähigen Merkmal (MF2), wobei der innere Schutzring (GR2) auf derselben Spannung (VOLT2) liegt wie das leitfähige Merkmal (MF2), wobei der äußere Schutzring (GR1) und der innere Schutzring (GR2) gleichzeitig auf unterschiedliche Spannungen (VOLT1, VOLT2) bringbar sind, wobei der innere Schutzring (GR2) und das leitfähige Merkmal (MF2) mittels einer elektrischen Verbindung (260) verbunden sind, undwobei das leifähige Merkmal (MF2) eine leitfähige Spule (610U) ist.

    18.
    发明专利
    未知

    公开(公告)号：DE10344388B4

    公开(公告)日：2006-06-08

    申请号：DE10344388

    申请日：2003-09-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KERBER MARTIN ,  HATZOPOULOS NIKOLAOS

    IPC: H01L21/336 ,  H01L21/28 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L29/51

    Abstract: A method eliminates effects of defects on wafers caused by cavities adjacent to the surface of a semiconductor (e.g., silicon) wafer. A first insulating layer is applied to the surface of the semiconductor wafer and into the cavities adjacent to the surface. The applied first insulating layer is covered with a sacrificial layer. A selective back-etching of the sacrificial layer is carried out, such that the cavities adjacent to the surface remain filled with the sacrificial layer. A second insulating layer is applied directly to the first insulating layer and, in a subsequent method step, a conducting layer is applied to the second insulating layer.

    20.
    发明专利
    未知

    公开(公告)号：ES2163045T3

    公开(公告)日：2002-01-16

    申请号：ES96938008

    申请日：1996-09-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KERBER MARTIN

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/788 ,  H01L29/792

    Abstract: The field insulation in a flash memory cell is provided by an oxide/polysilicon/oxide sandwich. The memory cell area is reduced by dopant implantation, self-aligned with respect to the word lines of two adjacent memory cells, for producing the source regions and source connections. The field insulation produces a capacitance between the doping region and the polysilicon layer of the insulation layer which improves the read characteristic of the memory cell.

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