公开(公告)号：JP2006179916A

公开(公告)日：2006-07-06

申请号：JP2005366627

申请日：2005-12-20

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： STECHER MATTHIAS

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/958 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor element for preventing any function from being damaged even when any crack is generated in a passivation layer, or for minimizing the damage of the function.
SOLUTION: This semiconductor element is provided with a semiconductor substrate (1); and a metal/insulator structure (2) arranged at the upper side of the semiconductor substrate (1), and equipped with a plurality of metallic regions (8
1 , 8
2 , 8
3 ) and an insulator region (10) adjacent to each other along the side face, wherein the metallic regions (8
1 , 8
2 , 8
3 ) play the role of the supply of currents to the semiconductor main body (1). The metal/insulator substrate is arranged at the upper side of the semiconductor substrate (1), and equipped with the plurality of metallic regions (8
1 , 8
2 , 8
3 ) and the insulator region (10) adjacent to each other along the side face. Furthermore, the semiconductor element is provided with a passivation layer (3) arranged on the metal/insulator structure (2). The passivation layer (3) is constituted of metal or a compound containing metal.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种半导体元件，用于防止任何功能即使在钝化层中产生任何裂纹或损坏功能时也不会损坏。 解决方案：该半导体元件设置有半导体衬底（1）; 以及设置在所述半导体基板（1）的上侧的金属/绝缘体结构（2），并且配备有多个金属区域（8＆lt; SB＆gt;，8＆lt; SB＆gt; 2＆lt; ，8＆lt; SB＆gt; 3）和沿着侧面彼此相邻的绝缘体区域（10），其中金属区域（8 8 2 ， 3 ）起到向半导体主体（1）供应电流的作用。 金属/绝缘体基板设置在半导体基板（1）的上侧，并且配备有多个金属区域（8＆lt; SB＆gt;，8＆lt; SB＆gt; 2＆lt; / SB＆ SB> 3 ）和沿侧面彼此相邻的绝缘体区域（10）。 此外，半导体元件设置有设置在金属/绝缘体结构（2）上的钝化层（3）。 钝化层（3）由金属或含金属的化合物构成。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO0135466A3

公开(公告)日：2001-11-22

申请号：PCT/EP0011090

申请日：2000-11-09

Applicant: INFINEON TECHNOLOGIES AG ,  HIRLER FRANZ ,  STECHER MATTHIAS ,  NELLE PETER ,  VIETZKE DIRK

Inventor： HIRLER FRANZ ,  STECHER MATTHIAS ,  NELLE PETER ,  VIETZKE DIRK

IPC: H01L21/205 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78 ,  H01L21/20

CPC classification number: H01L29/7813 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/161 ,  H01L29/167

Abstract: In order to prevent misfit caused by the high level of doping, the semiconductor substrate (1) of a field effect transistor, which comprises a body zone (3), is additionally doped with germanium or with carbon that serve to compensate for the misfit.

Abstract translation: 为了避免由于高掺杂失配，在半导体基板（1），其具有主体区（3）的场效应晶体管，另外掺杂有锗或碳作为补偿。

公开(公告)号：DE102004061307B4

公开(公告)日：2008-06-26

申请号：DE102004061307

申请日：2004-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STECHER MATTHIAS

IPC: H01L23/29 ,  H01L23/522

公开(公告)号：DE102006052202B3

公开(公告)日：2008-02-21

申请号：DE102006052202

申请日：2006-11-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTT THOMAS ,  SIEPE DIRK ,  LASKA THOMAS ,  MELZL MICHAEL ,  STECHER MATTHIAS ,  ROTH ROMAN

IPC: H01L23/485 ,  H01L21/28 ,  H01L21/60 ,  H01L23/52

Abstract: The component has a metal layer (1) comprising a coherent section. The other metal layer (2) is arranged on the coherent section of the former metal layer. The latter metal is harder than the former metal. The latter metal layer is structured between two layered regions (2a,2b) arranged on the coherent section of the former metal layer. The latter metal comprises boron or phosphorous containing metal and boron or phosphorous containing metal alloy. Independent claims are also included for the following: (1) a contact element comprising a layer pile with a continuous sub-area of a metallization layer of a semiconductor component (2) a method for producing a semiconductor component.

公开(公告)号：DE102006013203B3

公开(公告)日：2008-01-10

申请号：DE102006013203

申请日：2006-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STECHER MATTHIAS

IPC: H01L21/761 ,  H01L29/73 ,  H01L29/78

Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.

公开(公告)号：DE102007027378A1

公开(公告)日：2007-12-27

申请号：DE102007027378

申请日：2007-06-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOEGLAUER JOSEF ,  OTREMBA RALF ,  SCHLOEGEL XAVER ,  STECHER MATTHIAS

IPC: H01L23/482 ,  H01L21/445 ,  H01L21/58 ,  H01L23/12 ,  H01L29/78 ,  H05K1/18

Abstract: The arrangement has a vertical semiconductor diode (2) comprising a main surface (5). An electrically conductive substrate has a main surface (6), where a part of the main surface (6) presents in the direction of the main surface (5) and spaced at a distance to provide a recess. A galvanically applied metallic layer extends between the main surfaces and electrically connects the main surfaces. A spacer unit (11) is arranged in the recess to space the main surface (5) from the main surface (6). An independent claim is also included for a method of making a connection arrangement.

公开(公告)号：DE19953333B4

公开(公告)日：2004-07-15

申请号：DE19953333

申请日：1999-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NELLE PETER ,  SCHAEFER HERBERT ,  VIETZKE DIRK ,  STECHER MATTHIAS ,  BAUMGARTL JOHANNES ,  PERI HERMANN

IPC: H01L21/74 ,  H01L21/761 ,  H01L29/06

公开(公告)号：DE10303232A1

公开(公告)日：2003-08-28

申请号：DE10303232

申请日：2003-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DENISON MARIE ,  STECHER MATTHIAS ,  HOFMANN RENATE

IPC: H01L29/78

Abstract: The metal oxide semiconductor field effect transistor has a bulk trough with a highly doped diffusion source zone, a drain extension and a polysilicon gate plate on its upper side. The gate plate has an interruption in the region in which the bulk trough and drain extension lie adjacent to each other and an intermediate drain connecting zone as a connecting bridge between the bulk trough and drain extension in this region.. The metal oxide semiconductor field effect transistor has a bulk trough (43) of a bulk conductor type with a highly doped diffusion source zone (47) of a drain/source conductor type, a drain extension (31) and a polysilicon gate plate (30,40) on its upper side. The gate plate has an interruption (44) in the region in which the bulk trough and drain extension lie adjacent to each other and an intermediate drain connecting zone (39) as a connecting bridge between the bulk trough and drain extension in this region.

公开(公告)号：DE102010017483B4

公开(公告)日：2017-02-16

申请号：DE102010017483

申请日：2010-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STECHER MATTHIAS ,  WEBER HANS ,  O'RIAIN LINCOLN ,  EHRENWALL BIRGIT VON

IPC: H01L27/06 ,  H01L21/762 ,  H01L21/84 ,  H01L23/60 ,  H01L27/12 ,  H01L29/06

Abstract: Integrierte laterale Leistungsschaltung, umfassend einen Halbleiterkörper, umfassend: – eine erste und eine zweite Mulde von einem ersten Leitfähigkeitstyp, die sich zu einer ersten horizontalen Oberfläche erstrecken, wobei die zweite Mulde eine laterale Leistungshalbleiterstruktur umfasst, wobei die erste Mulde eine vergrabene Schicht vom ersten Leitfähigkeitstyp in einem unteren Abschnitt umfasst, wobei die vergrabene Schicht eine Dotierungskonzentration umfasst, die die Dotierungskonzentration eines angrenzenden oberen Abschnitts der ersten Mulde übersteigt; – ein erstes Halbleitergebiet von einem zweiten Leitfähigkeitstyp, das sich zu einer zweiten horizontalen Oberfläche erstreckt, die der ersten horizontalen Oberfläche gegenüberliegt; – eine Siliziumschicht, die zwischen der ersten Oberfläche und dem ersten Halbleitergebiet angeordnet ist, wobei die Siliziumschicht poly-Si und/oder amorphes Silizium umfasst; – ein Isoliergebiet, das die erste Mulde und die Siliziumschicht voneinander isoliert; und – einen vertikalen Graben, der die erste und zweite Mulde voneinander isoliert und sich von der ersten horizontalen Oberfläche mindestens zu dem Isoliergebiet erstreckt.

公开(公告)号：DE102009008504A1

公开(公告)日：2009-10-01

申请号：DE102009008504

申请日：2009-02-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SMORODIN TOBIAS ,  STECHER MATTHIAS

IPC: H01L29/78 ,  H01L21/336

Abstract: A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region. wherein the active region is interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller than an electrical power dissipation in the active region; and a metallization layer arranged with respect to the active region on a surface of the semiconductor device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the first terminal region, and a second part, in electrical contact to the second terminal region, wherein the first and the second part are separated by a gap; and wherein the gap and the inactive region are mutually arranged so that an electrical power dissipation below the gap is reduced compared to an electrical power dissipation below the first part and the second part of the metallization layer.