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    Method for arranging chips of first substrate on second substrate
    1.
    发明专利
    Method for arranging chips of first substrate on second substrate 有权
    用于在第二基板上安装第一基板的芯片的方法

    公开(公告)号：JP2005347760A

    公开(公告)日：2005-12-15

    申请号：JP2005164851

    申请日：2005-06-03

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： KERBER MARTIN

    IPC: H01L21/66 ,  H01L21/00 ,  H01L21/58 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

    CPC classification number: H01L23/544 ,  H01L21/67092 ,  H01L22/20 ,  H01L22/34 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To test simultaneously various chips of one substrate with improved economical efficiency.
    SOLUTION: The invention relates to a method for arranging chips (102-110) of a first substrate (100) on a second substrate (111). In this method, the chips are grouped into at least first chips (102) and second chips (103); the first chips (102) of the first substrate (100) are individualized; and individualized first chips (102) are arranged on the second substrate (111) in agreement, so that each of the first chips (102) is assigned uniquely to the first chips (102), belonging to the first substrate (100) on the second substrate (111).
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：同时测试一个基板的各种芯片，提高经济性。 解决方案：本发明涉及一种在第二基板（111）上布置第一基板（100）的芯片（102-110）的方法。 在这种方法中，芯片被分组成至少第一芯片（102）和第二芯片（103）; 第一基板（100）的第一芯片（102）被个性化; 并且个体化的第一芯片（102）被一致地布置在第二基板（111）上，使得第一芯片（102）中的每一个被唯一地分配给属于第一基板（100）上的第一芯片（102） 第二基板（111）。 版权所有（C）2006，JPO＆NCIPI

    Method for arranging chip of first substrate on second substrate
    2.
    发明专利
    Method for arranging chip of first substrate on second substrate 审中-公开
    用于在第二基板上安装第一基板的芯片的方法

    公开(公告)号：JP2009076924A

    公开(公告)日：2009-04-09

    申请号：JP2008271440

    申请日：2008-10-21

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： KERBER MARTIN

    IPC: H01L21/66 ,  H01L23/52 ,  G01R31/26 ,  H01L21/00 ,  H01L21/58 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

    CPC classification number: H01L23/544 ,  H01L21/67092 ,  H01L22/20 ,  H01L22/34 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To achieve the simultaneous examination of different chips of one substrate with increased economy.
    SOLUTION: A method for arranging the chips (102-110) of a first substrate (100) on a second substrate (111) is disclosed, in which the chips are grouped into at least first chips (102) and second chips (103), the first chips (102) of the first substrate (100) are individualized, and the individualized first chips (102) are arranged on the second substrate (111) in such a way that each of the first chips (102) on the second substrate (111) is unambiguously assigned to the associated first chip (102) on the first substrate (100).
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：实现同时检查一个基板的不同芯片，增加经济性。 公开了一种将第一基板（100）的芯片（102-110）布置在第二基板（111）上的方法，其中芯片被分组成至少第一芯片（102）和第二芯片 （103）中，第一基板（100）的第一芯片（102）被个体化，并且个体化的第一芯片（102）以这样的方式布置在第二基板（111）上，使得第一芯片（102） 在第二衬底（111）上被明确地分配给第一衬底（100）上的相关联的第一芯片（102）。 版权所有（C）2009，JPO＆INPIT

    SYSTEM FOR CONNECTION IN INTEGRATED MOS STRUCTURES
    4.
    发明申请
    SYSTEM FOR CONNECTION IN INTEGRATED MOS STRUCTURES 审中-公开
    安排连接集成MOS结构

    公开(公告)号：WO2005031866A2

    公开(公告)日：2005-04-07

    申请号：PCT/DE2004002002

    申请日：2004-09-09

    Applicant: INFINEON TECHNOLOGIES AG ,  KERBER MARTIN

    Inventor： KERBER MARTIN

    IPC: H01L23/525 ,  H01L23/528

    CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention relates to a system for connection in integrated MOS structures, wherein various levels and/or elements of a semiconductor chip are interconnected by means of connecting elements. The aim of the invention is to provide a system for connection in MOS structures which, when an affected element causes a high quadrature-axis component of current, allows for a reduction of current conduction or disconnection of the affected element. According to the invention, the connecting elements of the semiconductor chip are arranged and dimensioned in such a manner as to produce electromigration-critical areas by dimensioning a connection of various levels and/or the element in such a manner that electromigration is triggered when the current increases beyond a maximum value.

    Abstract translation: 本发明涉及到在不同的层和/或彼此连接的半导体芯片的元件所使用的连接元件，其目的是提供在MOS结构连接提供一种装置，用于在MOS集成结构连接的装置，它在的情况下 允许通过受影响的部件的高的横向流动，即减少的电流流动的或有关的元件的拆卸。 根据本发明，该目的是这样关键区域实现由电动迁移半导体芯片的连接元件的Layoutsund尺寸的布置各级产生通过化合物和/或尺寸设置成在元件使得电流的上升通过的最大值 电的过程中被触发。

    5.
    发明专利
    未知

    公开(公告)号：DE102007043336A1

    公开(公告)日：2008-04-03

    申请号：DE102007043336

    申请日：2007-09-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KERBER MARTIN

    IPC: H01L21/3065

    Abstract: Some embodiments discussed relate to an apparatus for etching a semiconductor wafer and method for fabricating it, comprising a plurality of electrodes coupled to a power supply for generating a plasma stream and at least one electromagnetic radiation source and a wafer support to position a wafer for etching using the plasma stream and the wafer support having a plurality of apertures to allow passage of electromagnetic radiation from an electromagnetic radiation source through the wafer support to impinge on a surface of the wafer during etching.

    6.
    发明专利
    未知

    公开(公告)号：DE59607841D1

    公开(公告)日：2001-11-08

    申请号：DE59607841

    申请日：1996-07-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KERBER MARTIN

    IPC: H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/092

    Abstract: In the proposed process, a masking layer (L) is deposited on the semiconductor material (1) and structured in the following way: a first region (6) where the contact is located is provided with an aperture (10) with an aspect ratio such that the aspect angle (20) between a diagonal and the normal onto the semiconductor material is less than an angle of incidence (30) onto the masking layer; in a second region where the doped region (7) is located, a ridge (12) of masking layer is left, the doped region being created by oblique implantation of atoms of a first conductivity at an implantation angle equivalent to the angle of incidence (30) and the contact (40) being formed by substantially vertical implantation of atoms of a second conductivity. The invention facilitates implantation of a mask onto a semiconductor well, the source and drain regions of the MOS transistors in the said well, and the contact regions of the complementary well.

    9.
    发明专利
    未知

    公开(公告)号：DE59913489D1

    公开(公告)日：2006-07-06

    申请号：DE59913489

    申请日：1999-03-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GSCHWANDTNER ALEXANDER ,  INNERTSBERGER GUDRUN ,  GRASSL ANDREAS ,  FROESCHLE BARBARA ,  KERBER MARTIN ,  MATTHEUS ALEXANDER

    IPC: H01L21/304 ,  H01L21/306 ,  H01L21/316

    Abstract: Fluorine is deposited on a semiconductor substrate surface according to a novel process. A semiconductor substrate is placed in a reaction chamber and the substrate surface is wetted with water and/or alcohol. A compound containing fluorine is led to the substrate surface, so that a cleaned semiconductor surface covered with fluorine is produced, and the compound containing fluorine is removed from the reaction chamber. The cleaned semiconductor surface covered with fluorine is then wetted with a mixture containing at least 10% by volume of water and at least 10% by volume of alcohol, for producing a cleaned semiconductor surface covered with a predetermined amount of fluorine. The predetermined amount of fluorine is lower the higher a proportion of water in the mixture is chosen to be. Then, the water and the alcohol are removed from the semiconductor surface.

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