公开(公告)号：DE10142682A1

公开(公告)日：2002-11-14

申请号：DE10142682

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN ,  BEER PETER

IPC: G11C5/14

Abstract: The module (1) comprises a memory component (2) with contact terminals (4,5,15,16) for voltage supply. On the module is located a circuit (6) for generating at least one voltage. The circuit is supplied with voltage via at least one contact terminal (4,5). The circuit contains one or more output lines (7-10) coupled to voltage input of the memory component. The circuit generates an internal voltage out of the supplied one and feeds it to the memory components via the output line. Independent claims are included for the memory component.

公开(公告)号：DE10063102A1

公开(公告)日：2001-08-23

申请号：DE10063102

申请日：2000-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BEER PETER ,  OHLHOFF CARSTEN

IPC: G01R19/165 ,  G01R31/28 ,  G11C29/00 ,  G01R31/3193

Abstract: The invention relates to a configuration for the measurement of internal voltages in a semiconductor device (2). A comparator (3) is provided in each DUT (2) and compares the internal voltage (Vint) to be measured with an externally supplied reference voltage (Vref). An independent claim is included for a testing method.

公开(公告)号：DE10135583B4

公开(公告)日：2004-05-06

申请号：DE10135583

申请日：2001-07-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN

IPC: G11C29/36 ,  G11C29/00 ,  G06F11/263

Abstract: A data generator for generating test data for a word-oriented semiconductor memory is integrated on a semiconductor chip of the semiconductor memory. The data generator has a shift register.

公开(公告)号：DE10226584C1

公开(公告)日：2003-11-13

申请号：DE10226584

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN ,  BEER PETER

IPC: G11C29/56 ,  G11C29/00

Abstract: The testing device (11) has a control interface (14) for connection with the memory circuit (DUT0-DUT15) to be tested and for reception of failed addresses and a failed address memory (18) for storing the failed addresses. A control unit (17) enters the failed addresses in the failed address memory, so that failed address received from the interface at a higher data rate are entered in memory cells accessed within a first access time and failed memory addresses received from the interface at a lower data rate are entered in memory cells accessed within a second access time, for delay-free storage of all failed addresses. Also included are Independent claims for the following: (a) a memory circuit testing system; (b) a memory circuit testing method

公开(公告)号：DE10214209A1

公开(公告)日：2003-10-23

申请号：DE10214209

申请日：2002-03-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN

IPC: G11C29/36 ,  G11C29/00

Abstract: The integrated memory has a memory cell field (3), a first data path (8-1,9-1) for reading data from the cell field, a second data path (6-1,9-1) for writing data to the cell field and an inverter stage (7-1) between the first and second data paths that activates the memory in test mode and connects the first and second data paths together in the activated state. AN Independent claim is also included for the following: a method of operating an inventive device.

公开(公告)号：DE10126301A1

公开(公告)日：2002-12-12

申请号：DE10126301

申请日：2001-05-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BEER PETER ,  OHLHOFF CARSTEN

IPC: G11C29/24 ,  G11C29/00

Abstract: The device has memory cells, an address circuit and test circuit connected to the address circuit. The test circuit outputs a signal to the address circuit in test mode and the address circuit activates a defective memory cell instead of a specified replacement cell if the signal from the test circuit is present and the address of the defective cell is applied. AN Independent claim is also included for the following: a method of testing memory cells of a repaired memory component.

公开(公告)号：DE10125022A1

公开(公告)日：2002-12-12

申请号：DE10125022

申请日：2001-05-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/08 ,  G11C29/12 ,  G11C29/14

Abstract: The invention relates to a dynamic memory having a memory cell array, a test controller to test the memory cell array and an oscillator to control the refreshing of the memory cell array. According to the invention, the memory includes a device for using the oscillator as a time base for the test controller, such that a slow time base is achieved which may be used for different self-tests of the memory.

公开(公告)号：DE102005007580A1

公开(公告)日：2006-08-31

申请号：DE102005007580

申请日：2005-02-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OSTENDORF HANS-CHRISTOPH ,  OHLHOFF CARSTEN ,  GOLLMER STEFAN

IPC: G01R31/319 ,  G11C29/56

Abstract: The device has a testing system for inputting test signals to an integrated circuit unit and evaluating response signals that are output by the unit based on input test signals. A tester circuit connects the unit to the system, and a connecting unit (104) arranged in the unit connects the circuit to circuit subunits. One of the subunits has a compression/decompression unit to exchange test and response signals between the subunits. An independent claim is also included for a method of testing an integrated circuit unit.

公开(公告)号：DE102004054874A1

公开(公告)日：2006-05-24

申请号：DE102004054874

申请日：2004-11-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN ,  OSTENDORF CHRISTOPH ,  GOLLMER STEFAN

IPC: G11C29/24

Abstract: An electronic circuit arrangement has a volatile memory unit (100), a non-volatile memory unit (200) and a connection device (300). The volatile memory unit (100) and the non-volatile memory unit (200) are designed as a single electronic module in which repair information concerning the volatile memory unit (100) is stored in the non-volatile memory unit (200). The volatile memory unit (100) is specifically a dynamic write-read store (DRAM).

公开(公告)号：DE50202486D1

公开(公告)日：2005-04-21

申请号：DE50202486

申请日：2002-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/08 ,  G11C29/12 ,  G11C29/14

Abstract: The invention relates to a dynamic memory having a memory cell array, a test controller to test the memory cell array and an oscillator to control the refreshing of the memory cell array. According to the invention, the memory includes a device for using the oscillator as a time base for the test controller, such that a slow time base is achieved which may be used for different self-tests of the memory.