Patent search ap:("INFINEON TECHNOLOGIES AG") AND inv:"OSTENDORF HANS-CHRISTOPH" Page 1

1.

发明专利
Memory circuit for data storage esp. for mobile/cell phone, has control circuit for blocking and enabling read/write functions in first and second state 未知

公开(公告)号：DE102004022792A1

公开(公告)日：2005-08-11

申请号：DE102004022792

申请日：2004-05-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OSTENDORF HANS-CHRISTOPH , ZIELBAUER JUERGEN

IPC: G11C7/20 , G11C11/4072

Abstract: A memory circuit (3) has a memory cells matrix (4), a control circuit (8) which is set into a first state with switch-on of the supply voltage to the memory circuit (3) and into a second state following initialization of the memory cells matrix (4). The control circuit (8), in the first state, blocks write and/or read of the memory cells matrix (4) and, in the second state, enables write and read of the memory cells matrix (4). An independent claim IS included for a method for driving a memory/storage circuit.

2.

发明专利
未知

公开(公告)号：DE10122081B4

公开(公告)日：2004-02-05

申请号：DE10122081

申请日：2001-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OSTENDORF HANS-CHRISTOPH

IPC: G01R31/319 , G11C29/56 , G01R35/00 , G11C29/00 , G01R31/3183

Abstract: A method and an apparatus provides for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a test signal in the form of a pattern of successive rising and falling edges, which is composed of superposed sub-patterns formed via different internal paths of the pattern generator. The pattern generator provides an information signal for a measuring device of the test system, which identifies the edges of at least one sub-pattern of the test signal with regard to their origin from one of the internal paths. The calibration is carried out for the internal path separately using the information signal.

3.

发明专利
Process and calibration device for testing semiconductor wafers automatically uses calibrating wafer to calibrate the device before inserting wafer to be tested 未知

公开(公告)号：DE10141025A1

公开(公告)日：2003-03-13

申请号：DE10141025

申请日：2001-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREBNER THOMAS , SCHITTENHELM MICHAEL , OSTENDORF HANS-CHRISTOPH , THALMANN ERWIN

IPC: G01R31/28 , G01R35/00 , H01L21/66

Abstract: A process for testing wafers in a test machine which can be calibrated automatically places a calibrating wafer (107) in the machine, calibrates it by means of a control unit and then inserts the wafer to be tested into the calibrated machine. An Independent claim is also included for a calibrating wafer for the above process.

4.

发明专利
Register information read out device e.g. for semiconductor chip identification 未知

公开(公告)号：DE19952947A1

公开(公告)日：2001-05-23

申请号：DE19952947

申请日：1999-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL , OSTENDORF HANS-CHRISTOPH

IPC: G06F11/00 , G11C7/10 , G11C7/00 , G11C29/00

Abstract: The read out device provides parallel read out of the register information held in a semiconductor chip using 2 or more input/output paths (I/O1,I/O2,...I/On), respectively associated with memory banks of the semiconductor chip via an input/output gating stage (2). The information is read out from the register, in which it is stored in the form of a number of fuses, via a multiplexer (4) operated in a test mode and line and column decoders (3,5) and entered in the memory banks via the input/output gating stage.

5.

发明专利
Verfahren zum Testen einer zu testenden Schaltungseinheit, welche Schaltungsuntereinheiten aufweist, und Testvorrichtung zur Durchführung des Verfahrens 未知

公开(公告)号：DE102005007580B4

公开(公告)日：2015-10-29

申请号：DE102005007580

申请日：2005-02-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OSTENDORF HANS-CHRISTOPH , OHLHOFF CARSTEN , GOLLMER STEFAN

IPC: G01R31/319 , G11C29/56

Abstract: Testvorrichtung zum Testen einer zu testenden Schaltungseinheit (101), welche Schaltungsuntereinheiten (102a–102n) aufweist, mit: a) einem Testsystem (200) zur Ausgabe von Testsignalen (201) zu der zu testenden Schaltungseinheit (101) und zum Auswerten von Antwortsignalen (202), die aus der zu testenden Schaltungseinheit (101) in Abhängigkeit von den dieser zugeführten Testsignalen (201) ausgegeben werden; b) einem Testerkanal (203) zum Anschließen der zu testenden Schaltungseinheit (101) an das Testsystem (200); und c) einer in der zu testenden Schaltungseinheit (101) angeordneten Verbindungseinheit (104) zum Verbinden des Testerkanals (203) mit den Schaltungsuntereinheiten (102a–102n) der zu testenden Schaltungseinheit (101), wobei mindestens eine erste Schaltungsuntereinheit (102a) ferner aufweist: d) eine erste Kompressions/Dekompressionseinheit (106a) zum Beschreiben der ersten Schaltungsuntereinheit (102a) in einem Dekompressionsmodus derart, dass die erste Schaltungsuntereinheit (102a) die Testsignale (201) erhält; dadurch gekennzeichnet, dass e) die der ersten Schaltungsuntereinheit (102a) der zu testenden Schaltungseinheit (101) von dem Testsystem (200) zugeführten Testsignale (201) in der ersten Kompressions/Dekompressionseinheit (106a) dekomprimiert werden; f) die erste Schaltungsuntereinheit (102a) in einen unkomprimierten Modus umschaltbar ist; g) mindestens eine zweite Schaltungsuntereinheit (102b) mit den dekomprimierten Testsignalen (201) aus der ersten Schaltungsuntereinheit (102a) beschrieben wird; h) Antwortsignale (202) aus der mindestens einen zweiten Schaltungsuntereinheit (102b) in die erste Schaltungsuntereinheit (102a) invertiert rückgeschrieben werden; und i) ein Kompressionsmodus durch die erste Kompressions/Dekompressionseinheit (106a) zum Auslesen der Antwortdaten (202) aus der ersten Schaltungsuntereinheit (102a) und zum Zuführen als Gesamt-Antwortdaten zu dem Testsystem (200) derart bereitgestellt wird, dass die aus der ersten Schaltungsuntereinheit (102a) der zu testenden Schaltungseinheit (101) ausgegebenen und dem Testsystem (200) zugefuhrten Antwortsignale (202) in der ersten Kompressions/Dekompressionseinheit (106a) komprimiert werden.

6.

发明专利
Integrated circuit with fuse memory permanently storing setting value for integrated circuit after integrated circuit testing 未知

公开(公告)号：DE10343388A1

公开(公告)日：2005-02-10

申请号：DE10343388

申请日：2003-09-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BEER PETER , OSTENDORF HANS-CHRISTOPH , SKALITZ MATTHIAS

IPC: G11C17/18 , G11C29/00 , G11C29/24

Abstract: The integrated circuit has a fuse memory (1) permanently storing a setting value for the integrated circuit, the latter brought into an output mode via a pre-defined setting value stored in the fuse memory, the setting value entered in the fuse memory after a programming step used for bringing the integrated circuit into an operating mode, with inactive switching of the fuse memory after the programming step by a switching device (8). A test circuit (9) switches the fuse memory into its inactive state upon a test mode, so that the integrated circuit is operated in its output mode with the pre-defined setting value.

7.

发明专利
Calibration of test cards that form part of a test system for carrying out of wafer tests, using a device that is suitable for calibrating test cards with unsprung contact elements 未知

公开(公告)号：DE10116823A1

公开(公告)日：2002-11-07

申请号：DE10116823

申请日：2001-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HUEBNER MICHAEL , VASQUEZ BARBARA , OSTENDORF HANS-CHRISTOPH

IPC: G01R35/00 , G01R31/28 , H01L21/66

Abstract: Device for calibrating test cards (100') with unsprung contact elements (50') that are used to test semiconductor wafers has: a probe arrangement (200') that has first (KSIG') and second (KSCH') signal contact surfaces; and a positioning device for positioning the probe device on the test card so that first and second signal contact surfaces connect to first and second test card contact elements (50'); whereby the first and second contact surfaces are attached in a sprung manner to the probe arrangement.

8.

发明专利
未知

公开(公告)号：DE10141025B4

公开(公告)日：2007-05-24

申请号：DE10141025

申请日：2001-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREBNER THOMAS , SCHITTENHELM MICHAEL , OSTENDORF HANS-CHRISTOPH , THALMANN ERWIN

IPC: H01L21/66 , G01R31/28 , G01R35/00

Abstract: The invention provides a method for testing wafers ( 101 ) to be tested in a test device ( 100 ), in which the test device ( 100 ) can be calibrated, at least one calibration wafer ( 102 ) being automatically introduced into the test device ( 100 ) by means of a handling unit ( 103 ), calibration values of the test device ( 100 ) being determined by means of a control by a calibration sequence control unit ( 105 ), the calibration values determined being stored in a memory unit ( 106 ), the test device ( 100 ) being calibrated by means of the stored calibration values, the calibration wafer ( 102 ) being output from the calibrated test device ( 100 ), and at least one wafer ( 101 ) to be tested being introduced into the calibrated test device ( 100 ) by means of the handling unit ( 103 ) and being tested by a control by means of a test sequence control unit ( 104 ) in the calibrated test device ( 100 ), the stored calibration values being applied.

9.

发明专利
未知

公开(公告)号：DE10116823C2

公开(公告)日：2003-10-30

申请号：DE10116823

申请日：2001-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HUEBNER MICHAEL , VASQUEZ BARBARA , OSTENDORF HANS-CHRISTOPH

IPC: G01R35/00 , G01R31/28 , H01L21/66 , H01R11/00

10.

发明专利
未知

公开(公告)号：DE19952947B4

公开(公告)日：2007-02-01

申请号：DE19952947

申请日：1999-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUND MICHAEL , OSTENDORF HANS-CHRISTOPH

IPC: G11C7/00 , G06F11/00 , G11C7/10 , G11C29/00

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