公开(公告)号：JP2001216040A

公开(公告)日：2001-08-10

申请号：JP2000377689

申请日：2000-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN

IPC: H01L27/04 ,  G05F3/24 ,  G11C5/14 ,  G11C7/14 ,  H01L21/66 ,  H01L21/822 ,  H01L23/544

Abstract: PROBLEM TO BE SOLVED: To provide a device for adjusting a reference voltage quickly and inexpensively adjusting a reference voltage to be generated by semiconductor chips arranged on a semiconductor wafer so as to be made equal to all the semiconductor chips on the semiconductor wafer, and made suitable for an outside voltage as each target value of the reference voltage by using correction information by comparing a reference voltage Vref with a voltage Vvg1 supplied from the outside part in a test program. SOLUTION: A semiconductor chip is provided with a test logic 2 post connected to a voltage comparator 1, and the voltage comparator compares a voltage Vvg1 with a reference voltage Vref-trim supplied from an adjusting circuit 4 and changed by the adjusting circuit.

公开(公告)号：WO02095756A3

公开(公告)日：2003-05-08

申请号：PCT/EP0205244

申请日：2002-05-13

Applicant: INFINEON TECHNOLOGIES AG ,  OHLHOFF CARSTEN

Inventor： OHLHOFF CARSTEN

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/08 ,  G11C29/12 ,  G11C29/14

CPC classification number: G11C29/12015 ,  G11C11/401 ,  G11C29/14

Abstract: The invention relates to a dynamic memory comprising a memory cell array (10), a test controller (12) for testing the memory cell array (10) and an oscillator (14) for controlling the refreshing of said memory cell array (10). According to the invention, said memory includes means (16) for using the oscillator (14) as a time base for the test controller. Hereby, a slow time base is achieved, which may be used for different self-tests of the memory.

Abstract translation: 本发明涉及一种具有用于测试的存储单元阵列（10）和振荡器（14），用于控制存储单元阵列（10）的刷新的存储单元阵列（10）的测试控制器（12）动态存储器。 根据本发明的存储器包括用于所述振荡器（14）作为用于测试控制器的时基的益处装置（16）。 这也提供了可用于存储器的各种自检一个“慢”时基。

公开(公告)号：DE19936321C2

公开(公告)日：2003-12-24

申请号：DE19936321

申请日：1999-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN

IPC: H01L23/544 ,  H01L21/66

Abstract: Arrangement and method for testing a multiplicity of semiconductor chips at the wafer level The invention relates to an arrangement and a method for testing a multiplicity of semiconductor chips (7) at the wafer level, in which an intermediate wiring plane (10) with a global test bus (12) and test pads (11) is applied to the surface of the wafer (6).

公开(公告)号：DE10204688C1

公开(公告)日：2003-10-09

申请号：DE10204688

申请日：2002-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BEER PETER ,  OHLHOFF CARSTEN ,  SCHNEIDER HELMUT

IPC: G11C11/401 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L31/119

Abstract: A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. First electrodes of the dummy memory cells are connected to a reference potential. A counter electrode of the dummy memory cells is electrically connected to the counter electrode of the memory cells. A charge capacitance of the counter electrode of the memory cells is increased in this way. Consequently, there is an overall increase in the voltage stability of the memory module with respect to a large entry of charge into the memory cells.

公开(公告)号：DE10245551A1

公开(公告)日：2004-04-08

申请号：DE10245551

申请日：2002-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN ,  BEER PETER

IPC: G01R15/20 ,  G01R19/00 ,  H01L23/58 ,  H01L43/06

Abstract: To measure the current consumption of a circuit device with a current measuring device, the circuit device being supplied by a current/voltage supply line device, as simply as possible without the need for additional measuring devices, an integrated circuit configuration includes integrating the circuit configuration, the current measuring device, and, also, the current/voltage supply line device in a common chip and forming the current measuring device with a Hall sensor device.

公开(公告)号：DE10229802B3

公开(公告)日：2004-01-08

申请号：DE10229802

申请日：2002-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN ,  BEER PETER

IPC: G11C29/40 ,  G11C29/00

Abstract: A test circuit for testing a memory circuit has a data input line for providing test data and a comparator unit. The comparator unit is connected to the data input line and to the memory circuit for comparing the test data written into the memory circuit with the test data read from the memory area. The data input line is connected to the memory circuit via a data change circuit. The data change circuit is controllable depending on a result of a comparison in the comparator unit such that when an error occurs, subsequent test data can be written in an altered manner to the memory circuit.

公开(公告)号：DE10125164C1

公开(公告)日：2003-01-16

申请号：DE10125164

申请日：2001-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN ,  BEER PETER

IPC: G11C29/02 ,  H01L23/58 ,  G11C29/00 ,  H03B5/00

公开(公告)号：DE102005007580B4

公开(公告)日：2015-10-29

申请号：DE102005007580

申请日：2005-02-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OSTENDORF HANS-CHRISTOPH ,  OHLHOFF CARSTEN ,  GOLLMER STEFAN

IPC: G01R31/319 ,  G11C29/56

Abstract: Testvorrichtung zum Testen einer zu testenden Schaltungseinheit (101), welche Schaltungsuntereinheiten (102a–102n) aufweist, mit: a) einem Testsystem (200) zur Ausgabe von Testsignalen (201) zu der zu testenden Schaltungseinheit (101) und zum Auswerten von Antwortsignalen (202), die aus der zu testenden Schaltungseinheit (101) in Abhängigkeit von den dieser zugeführten Testsignalen (201) ausgegeben werden; b) einem Testerkanal (203) zum Anschließen der zu testenden Schaltungseinheit (101) an das Testsystem (200); und c) einer in der zu testenden Schaltungseinheit (101) angeordneten Verbindungseinheit (104) zum Verbinden des Testerkanals (203) mit den Schaltungsuntereinheiten (102a–102n) der zu testenden Schaltungseinheit (101), wobei mindestens eine erste Schaltungsuntereinheit (102a) ferner aufweist: d) eine erste Kompressions/Dekompressionseinheit (106a) zum Beschreiben der ersten Schaltungsuntereinheit (102a) in einem Dekompressionsmodus derart, dass die erste Schaltungsuntereinheit (102a) die Testsignale (201) erhält; dadurch gekennzeichnet, dass e) die der ersten Schaltungsuntereinheit (102a) der zu testenden Schaltungseinheit (101) von dem Testsystem (200) zugeführten Testsignale (201) in der ersten Kompressions/Dekompressionseinheit (106a) dekomprimiert werden; f) die erste Schaltungsuntereinheit (102a) in einen unkomprimierten Modus umschaltbar ist; g) mindestens eine zweite Schaltungsuntereinheit (102b) mit den dekomprimierten Testsignalen (201) aus der ersten Schaltungsuntereinheit (102a) beschrieben wird; h) Antwortsignale (202) aus der mindestens einen zweiten Schaltungsuntereinheit (102b) in die erste Schaltungsuntereinheit (102a) invertiert rückgeschrieben werden; und i) ein Kompressionsmodus durch die erste Kompressions/Dekompressionseinheit (106a) zum Auslesen der Antwortdaten (202) aus der ersten Schaltungsuntereinheit (102a) und zum Zuführen als Gesamt-Antwortdaten zu dem Testsystem (200) derart bereitgestellt wird, dass die aus der ersten Schaltungsuntereinheit (102a) der zu testenden Schaltungseinheit (101) ausgegebenen und dem Testsystem (200) zugefuhrten Antwortsignale (202) in der ersten Kompressions/Dekompressionseinheit (106a) komprimiert werden.

公开(公告)号：DE19930169B4

公开(公告)日：2004-09-30

申请号：DE19930169

申请日：1999-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN ,  POECHMUELLER PETER

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/12 ,  G11C29/16 ,  G11C29/56 ,  H01L21/66 ,  G01R31/3187

Abstract: A substrate includes a memory and a testing device for testing the memory. The testing device includes an interpreter element that operates and tests the memory in accordance with a test program. The test program command codes are stored in the untested memory cell array of the memory that will be tested. The advantage of the testing device consists, inter alia, in the fact that the testing device no longer needs to be adapted to changed hardware properties of the chip generation or fabrication lines because the test program, which is suitable for the respective chip type, is stored as a variable code on the respective memory which is to be tested. It is thus also possible to test various memory chip types with the same testing device.

公开(公告)号：DE10135583A1

公开(公告)日：2003-02-13

申请号：DE10135583

申请日：2001-07-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OHLHOFF CARSTEN

IPC: G11C29/36 ,  G11C29/00 ,  G06F11/263

Abstract: A data generator for generating test data for a word-oriented semiconductor memory is integrated on a semiconductor chip of the semiconductor memory. The data generator has a shift register.