12.
    发明专利
    未知

    公开(公告)号:DE10122081A1

    公开(公告)日:2002-12-12

    申请号:DE10122081

    申请日:2001-05-07

    Abstract: A method and an apparatus provides for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a test signal in the form of a pattern of successive rising and falling edges, which is composed of superposed sub-patterns formed via different internal paths of the pattern generator. The pattern generator provides an information signal for a measuring device of the test system, which identifies the edges of at least one sub-pattern of the test signal with regard to their origin from one of the internal paths. The calibration is carried out for the internal path separately using the information signal.

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