公开(公告)号：DE10358556A1

公开(公告)日：2004-08-05

申请号：DE10358556

申请日：2003-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  KANG WOO-TAG ,  SEITZ MIHEL

IPC: H01L21/283 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L27/10 ,  H01L31/119

Abstract: A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.

公开(公告)号：DE10244987A1

公开(公告)日：2003-05-28

申请号：DE10244987

申请日：2002-09-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RAMACHANDRAN RAVIKUMAR ,  SEITZ MIHEL

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/4763

Abstract: In a method of making a W/WN/Poly-Gatestack, the improvement of providing low temperature sidewall oxidation to affect less outdiffusion of dopant implants near the surface to allow more margin in small groundrule device design for a support device, comprising:depositing a silicon layer on a substrate; forming a W-containing nitride layer on the deposited silicon;depositing a W layer on the W-containing nitride layer to form a W/WN/silicon stack; andperforming a gatesidewall anodic oxidation by affecting a mask open to enable contacting W at its wafer edge and putting the gatestack on the positive potential or anode and the counter electrode on the negative potential.

公开(公告)号：DE10228717A1

公开(公告)日：2003-01-30

申请号：DE10228717

申请日：2002-06-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEITZ MIHEL

IPC: H01L21/762

Abstract: A method of providing isolation between active areas of memory cells in a memory device having a plurality of isolation trenches (115) separating the active areas, comprising depositing a first insulating material (116) and forming a resist (120) over the first insulating material (116) over at least the trenches (115), leaving a first top portion of the first insulating material (116) exposed. At least a second top portion of the first insulating material (116) is removed, the resist (120) is removed, and a second insulating material (216) is deposited over the wafer (100) to completely fill the isolation trenches (115).