公开(公告)号：DE10320598A1

公开(公告)日：2004-01-08

申请号：DE10320598

申请日：2003-05-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEE KIL-HO ,  KANG WOO-TAG

IPC: H01L21/336 ,  H01L29/78

Abstract: A method of manufacturing a transistor by using two layers of a silicon epitaxial layer is disclosed. In the first step of the manufacturing process, a spacer is formed around gate structures. Then, a first silicon epitaxial layer is grown on the wafer. Then, a second spacer is deposited and then etched, such that the second spacer remains around a gate structure. Next a second silicon epitaxial layer is grown on the first silicon epitaxial layer, and the second spacer is etched from around the gate structure. After etching the first oxide spacer, ions are implanted at a first energy level to form four junctions. Then a third spacer is deposited and etched, so that the third spacer remains around the gate structures. Then ions are implanted at a second energy level to form two more junctions, each of these two junctions being located between two of the earlier formed junctions. The junctions and the gate structures provide a transistor structure. The resulting transistor has a good short channel effect because the junction depths are preferably all aligned. It also has good drive current because the junctions created by ion implantation at a second energy level have low parasitic resistance.

公开(公告)号：DE10253900A1

公开(公告)日：2003-06-18

申请号：DE10253900

申请日：2002-11-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KANG WOO-TAG ,  LEE KIL-HO ,  RENGARAJAN RAJESH

IPC: H01L21/8238 ,  H01L21/336

Abstract: In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate electrode so that there is no boron penetration in the channel region and no boron depletion near the gate oxide, comprising:a) forming a gate oxide layer over a channel of a nMOS site and over a channel of a pMOS site;b) forming an undoped polysilicon layer over the gate oxide layer;c) masking the pMOS site, forming an a-Si layer over the nMOS site using a first heavy ion implantation, and implanting arsenic solely into the a-Si layer;d) masking the nMOS site formed by step c), forming an a-Si layer over the pMOS site using a second heavy ion implantation, and implanting boron solely into the a-Si regions;e) laser annealing the nMOS and pMOS sites for a short time and at an energy level sufficient to melt at least a portion of the a-Si but insufficient to melt the polysilicon; andf) affecting cooling after laser annealing to convert a-Si into polysilicon without gate oxide damage.

公开(公告)号：DE10320598B4

公开(公告)日：2007-02-01

申请号：DE10320598

申请日：2003-05-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEE KIL-HO ,  KANG WOO-TAG

IPC: H01L21/336 ,  H01L29/78

Abstract: A method of manufacturing a transistor by using two layers of a silicon epitaxial layer is disclosed. In the first step of the manufacturing process, a spacer is formed around gate structures. Then, a first silicon epitaxial layer is grown on the wafer. Then, a second spacer is deposited and then etched, such that the second spacer remains around a gate structure. Next a second silicon epitaxial layer is grown on the first silicon epitaxial layer, and the second spacer is etched from around the gate structure. After etching the first oxide spacer, ions are implanted at a first energy level to form four junctions. Then a third spacer is deposited and etched, so that the third spacer remains around the gate structures. Then ions are implanted at a second energy level to form two more junctions, each of these two junctions being located between two of the earlier formed junctions. The junctions and the gate structures provide a transistor structure. The resulting transistor has a good short channel effect because the junction depths are preferably all aligned. It also has good drive current because the junctions created by ion implantation at a second energy level have low parasitic resistance.

公开(公告)号：DE10358556A1

公开(公告)日：2004-08-05

申请号：DE10358556

申请日：2003-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  KANG WOO-TAG ,  SEITZ MIHEL

IPC: H01L21/283 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L27/10 ,  H01L31/119

Abstract: A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.