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    METHOD FOR FORMING AND FILLING ISOLATION TRENCHES
    1.
    发明申请
    METHOD FOR FORMING AND FILLING ISOLATION TRENCHES 审中-公开
    形成和填充隔离开口的方法

    公开(公告)号：WO0243111A3

    公开(公告)日：2002-08-01

    申请号：PCT/EP0113436

    申请日：2001-11-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MALIK RAJEEV ,  SEITZ MIHEL ,  KNORR ANDREAS

    IPC: H01L21/762 ,  H01L21/8242

    CPC classification number: H01L21/76229 ,  H01L27/1087

    Abstract: A method for forming isolation trenches for semiconductor devices forms, in a substrate, a plurality of trenches (30 and 32) having different widths including widths above a threshold size (30) and widths below a threshold size (32). The plurality of trenches have a same first depth (D1). A masking layer (52) is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate (16) is exposed at a bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches are etched to extend the trenches with the widths above the threshold size to a greater depth (D2).

    Abstract translation: 一种用于形成半导体器件的隔离沟槽的方法在衬底中形成具有不同宽度的多个沟槽（30和32），所述宽度包括高于阈值尺寸（30）和低于阈值尺寸（32）的宽度。 多个沟槽具有相同的第一深度（D1）。 在多个沟槽中沉积掩模层（52），掩模层的厚度足以使沟槽的宽度高于阈值尺寸，并且完全填充宽度低于阈值尺寸的沟槽。 通过蚀刻掩模层，衬底（16）的一部分在沟槽的底部暴露，其宽度高于阈值尺寸。 蚀刻多个沟槽以使沟槽的宽度高于阈值尺寸延伸到更大的深度（D2）。

    3.
    发明专利
    未知

    公开(公告)号：DE10354937A1

    公开(公告)日：2004-06-17

    申请号：DE10354937

    申请日：2003-11-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROBL WERNER ,  SEITZ MIHEL ,  GOEBEL THOMAS ,  MALIK RAJEEV

    IPC: H01L21/768 ,  H01L21/8242 ,  H01L21/285

    Abstract: A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300° C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300° C.

    9.
    发明专利
    未知

    公开(公告)号：DE10358556A1

    公开(公告)日：2004-08-05

    申请号：DE10358556

    申请日：2003-12-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MALIK RAJEEV ,  KANG WOO-TAG ,  SEITZ MIHEL

    IPC: H01L21/283 ,  H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L27/10 ,  H01L31/119

    Abstract: A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.

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