公开(公告)号：WO0243111A3

公开(公告)日：2002-08-01

申请号：PCT/EP0113436

申请日：2001-11-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  SEITZ MIHEL ,  KNORR ANDREAS

IPC: H01L21/762 ,  H01L21/8242

CPC classification number: H01L21/76229 ,  H01L27/1087

Abstract: A method for forming isolation trenches for semiconductor devices forms, in a substrate, a plurality of trenches (30 and 32) having different widths including widths above a threshold size (30) and widths below a threshold size (32). The plurality of trenches have a same first depth (D1). A masking layer (52) is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate (16) is exposed at a bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches are etched to extend the trenches with the widths above the threshold size to a greater depth (D2).

Abstract translation: 一种用于形成半导体器件的隔离沟槽的方法在衬底中形成具有不同宽度的多个沟槽（30和32），所述宽度包括高于阈值尺寸（30）和低于阈值尺寸（32）的宽度。 多个沟槽具有相同的第一深度（D1）。 在多个沟槽中沉积掩模层（52），掩模层的厚度足以使沟槽的宽度高于阈值尺寸，并且完全填充宽度低于阈值尺寸的沟槽。 通过蚀刻掩模层，衬底（16）的一部分在沟槽的底部暴露，其宽度高于阈值尺寸。 蚀刻多个沟槽以使沟槽的宽度高于阈值尺寸延伸到更大的深度（D2）。

公开(公告)号：DE10354937A1

公开(公告)日：2004-06-17

申请号：DE10354937

申请日：2003-11-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROBL WERNER ,  SEITZ MIHEL ,  GOEBEL THOMAS ,  MALIK RAJEEV

IPC: H01L21/768 ,  H01L21/8242 ,  H01L21/285

Abstract: A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300° C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300° C.

公开(公告)号：DE10350703A1

公开(公告)日：2004-05-27

申请号：DE10350703

申请日：2003-10-30

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MANDELMAN JACK A ,  CHUDZIK MICHAEL ,  SEITZ MIHEL

IPC: H01L27/108 ,  H01L21/329 ,  H01L21/8242 ,  H01L29/94

Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.

公开(公告)号：DE102004052644A1

公开(公告)日：2006-05-04

申请号：DE102004052644

申请日：2004-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEITZ MIHEL ,  DETERS RIA

IPC: H01L21/308

Abstract: A shadowing unit (1) for the edge region (21) of a semiconductor wafer (2), to protect the substrate in the edge region during etching, comprises a protective layer (11). The latter is applied to the substrate, and can be removed selectively.

公开(公告)号：DE102004012280A1

公开(公告)日：2005-10-06

申请号：DE102004012280

申请日：2004-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEGE STEPHAN ,  SEITZ MIHEL

IPC: H01L21/308 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108

Abstract: The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate ( 1 ) made of silicon with a first hard mask layer ( 10; 10' ) made of silicon oxide and an overlying second hard mask layer ( 15; 15' ) made of silicon; providing a masking layer ( 30; 30' ) made of silicon oxide above and laterally with respect to the second hard mask layer ( 15; 15' ) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate ( 1 ); providing a photoresist mask ( 25 ) above the masking layer ( 30; 30' ) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate ( 1 ); opening the masking layer ( 30; 30' ) in a first plasma process using the photoresist mask ( 25 ), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer ( 10; 10' ) and second hard mask layer ( 15; 15' ) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate ( 1 ) in a fourth plasma process using the opened first hard mask layer ( 10; 10' ); the edge region (RB) not being covered by the shielding device (AR) in the second to fourth plasma processes.

公开(公告)号：DE10353269B3

公开(公告)日：2005-05-04

申请号：DE10353269

申请日：2003-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOLL HANS-PETER ,  HEINECK LARS ,  SEITZ MIHEL ,  KUNDALGURKI SRIVATSA

IPC: H01L21/334 ,  H01L21/8242

Abstract: The production of a trench capacitor with an insulation collar (sic) in a substrate, which is electrically connected to the substrate via a trenched (sic) contact, especially for a semiconductor storage cell, and a selection transistor involves the provision of a trench in the substrate using a hard mask, a capacitor dielectric, an Si oxide liner, formation of a liner mask from part of the liner, and provision of an upper liner from undoped poly-Si or amorphous Si.

公开(公告)号：DE102004012280B4

公开(公告)日：2005-12-29

申请号：DE102004012280

申请日：2004-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEGE STEPHAN ,  SEITZ MIHEL

IPC: H01L21/308 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108

Abstract: The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate ( 1 ) made of silicon with a first hard mask layer ( 10; 10' ) made of silicon oxide and an overlying second hard mask layer ( 15; 15' ) made of silicon; providing a masking layer ( 30; 30' ) made of silicon oxide above and laterally with respect to the second hard mask layer ( 15; 15' ) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate ( 1 ); providing a photoresist mask ( 25 ) above the masking layer ( 30; 30' ) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate ( 1 ); opening the masking layer ( 30; 30' ) in a first plasma process using the photoresist mask ( 25 ), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer ( 10; 10' ) and second hard mask layer ( 15; 15' ) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate ( 1 ) in a fourth plasma process using the opened first hard mask layer ( 10; 10' ); the edge region (RB) not being covered by the shielding device (AR) in the second to fourth plasma processes.

公开(公告)号：DE10345461B3

公开(公告)日：2005-08-11

申请号：DE10345461

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOUBEKEUR HOCINE ,  SEITZ MIHEL

IPC: H01L21/8242

Abstract: The method involves providing a substrate (1) from substrate material, forming a trench (2) with a trench wall (21) in the substrate from the substrate surface, covering the lower section (212) of the trench wall below a collar edge (30) with a passivation layer (4) of mask material and selectively coating an upper section (211) of the trench wall above the collar lower edge with a process layer (3) to the lower section, whereby the substrate is repeatedly alternately exposed to at least two different process fluids. Independent claims are also included for the following: (A) a method of forming a collar structure in an upper section of a semiconductor substrate (B) and a method of manufacturing a storage capacitor for a memory cell.

公开(公告)号：DE102004002205B3

公开(公告)日：2005-06-23

申请号：DE102004002205

申请日：2004-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEITZ MIHEL ,  SACHSE HERMANN ,  MOLL HANS-PETER ,  FROEHLICH HANS-GEORG ,  VOIGT INA

IPC: H01L21/8242 ,  H01L23/544

Abstract: A semiconductor wafer with substrate (5) is prepared. A deep trench (12) and at least one depression are formed in the substrate. An external capacitor electrode is formed in the lower region of the trench (12). Dielectric is deposited in the lower region of the trench. An inner capacitor electrode is formed by filling the lower region only, with conductive material. A collar (42) is formed in the upper region of the side walls of the trench and the depression. Trench and depression are filled in the upper region with filling material (48), so that in the region of the depression a hollow representing the alignment mask remains. A semiconductor wafer with substrate (5) is prepared. A deep trench (12) and at least one depression are formed in the substrate. An external capacitor electrode is formed in the lower region of the trench (12). Dielectric is deposited in the lower region of the trench. An inner capacitor electrode is formed by filling the lower region only, with conductive material. A collar (42) is formed in the upper region of the side walls of the trench and the depression. Trench and depression are filled in the upper region with filling material (48), so that in the region of the depression a hollow representing the alignment mask remains. A liner layer (16) is deposited completely over the whole area of the substrate (5). Full-area deposition of a non-doped amorphous silicon layer follows, over the liner layer. A resist layer is deposited over the non-doped amorphous silicon layer. The resist layer is structured so that the upper side of the semiconductor wafer is covered by it, in the region of the hollow. Angled implantation of a dopant follows, forming a doped amorphous silicon layer. The resist layer is removed. Selective etching of the non-doped amorphous silicon layer, bares the underlying liner layer. This is then removed and the filling material in the trench and in the depression is etched. An independent claim is included for the corresponding semiconductor arrangement with alignment mask and trench capacitor.

公开(公告)号：DE10228717B4

公开(公告)日：2007-11-22

申请号：DE10228717

申请日：2002-06-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEITZ MIHEL

IPC: H01L21/762 ,  H01L21/8242 ,  H01L21/8247

Abstract: A method of providing isolation between active areas of memory cells in a memory device having a plurality of isolation trenches (115) separating the active areas, comprising depositing a first insulating material (116) and forming a resist (120) over the first insulating material (116) over at least the trenches (115), leaving a first top portion of the first insulating material (116) exposed. At least a second top portion of the first insulating material (116) is removed, the resist (120) is removed, and a second insulating material (216) is deposited over the wafer (100) to completely fill the isolation trenches (115).