公开(公告)号：DE10030696A1

公开(公告)日：2002-01-10

申请号：DE10030696

申请日：2000-06-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUETZEN JOERN ,  SELL BERNHARD

IPC: H01L21/8242 ,  H01L21/762 ,  H01L27/108

Abstract: Integrated circuit comprises: a switching element (AT) formed in a substrate (1); a switching element (160) buried in the substrate away from the element (AT); and an insulating layer (7) lying between the elements and locally limited in the substrate. An Independent claim is also included for a process for the production of an integrated circuit, comprising forming trenches (10) in a substrate (1), forming an outer conducting layer on lower regions of the trenches within the substrate as first capacitor plates, forming dielectric layers in the trenches as capacitor dielectric, forming an inner conducting layer (5) in the trenches as second capacitor plates, and forming insulating areas (7) on wall sections of the trenches above the outer conducting layer. Preferred Features: The insulating layer is a thermal oxide. The substrate is a single crystalline semiconductor substrate.

公开(公告)号：DE50014010D1

公开(公告)日：2007-03-15

申请号：DE50014010

申请日：2000-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHUMANN DIRK ,  SELL BERNHARD ,  WILLER JOSEF

IPC: H01L21/00 ,  H01L21/8242 ,  H01L21/02 ,  H01L27/108

公开(公告)号：DE50013949D1

公开(公告)日：2007-02-22

申请号：DE50013949

申请日：2000-03-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLER JOSEF ,  CAPPELLANI ANNALISA ,  SELL BERNHARD

IPC: H01L21/8242 ,  H01L21/285 ,  H01L21/768 ,  H01L27/108

Abstract: The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.

公开(公告)号：DE10030696B4

公开(公告)日：2006-04-06

申请号：DE10030696

申请日：2000-06-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUETZEN JOERN ,  SELL BERNHARD

IPC: H01L21/762 ,  H01L21/8242 ,  H01L27/108

Abstract: The integrated circuit configuration has at least one buried circuit element and an insulating layer. A multiplicity of insulating regions are in contact with one another to forming a locally delimited insulating layer in the substrate. In this way, trench capacitors implemented as buried circuit elements can be manufactured with a structure size of less than 100 nm in a simple and cost-effective manner.

公开(公告)号：DE19947082B4

公开(公告)日：2005-02-10

申请号：DE19947082

申请日：1999-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  WILLER JOSEF ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L21/02 ,  H01L27/108

Abstract: A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).

公开(公告)号：DE10208450B4

公开(公告)日：2004-09-16

申请号：DE10208450

申请日：2002-02-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAENGER ANNETTE ,  SELL BERNHARD ,  SEIDL HARALD ,  HECHT THOMAS ,  GUTSCHE MARTIN

IPC: C23C16/34 ,  C23C16/40 ,  C23C16/42 ,  C23C16/44 ,  C23C16/455 ,  C23C16/46 ,  C23C16/48 ,  C23C16/30

Abstract: Process chamber for producing a layer of material on sections of a surface (8) of a substrate (3) comprises: holding unit (2) for substrate; feeding and removal units (6) for gas phases of chemical precursors of the layer material; substrate feeding device (11) for introducing substrate into process chamber; heating source (9) for heating the substrate and/or substrate surface; and control unit. The control unit is used for sequentially introducing the chemical precursor compounds. The heating source (9) is formed as a radiation source, by means of which the temperature on the substrate surface can be changed in steps of more than 100 K per second. The radiation source is a heating lamp and is arranged in the chamber inner chamber (5) of the process chamber enclosed by a chamber wall (4). An Independent claim is also included for a process for depositing a layer of material on sections of a surface of a substrate.

公开(公告)号：DE10128481B4

公开(公告)日：2004-01-08

申请号：DE10128481

申请日：2001-06-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  SELL BERNHARD ,  HECHT THOMAS

IPC: B44C1/22 ,  C03C25/68 ,  G03F7/26 ,  H01L21/308 ,  H01L21/31

Abstract: An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.

公开(公告)号：DE10156932A1

公开(公告)日：2003-05-28

申请号：DE10156932

申请日：2001-11-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAENGER ANNETTE DR ,  GUTSCHE MARTIN DR ,  SEIDL HARALD ,  SELL BERNHARD

IPC: C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/51

Abstract: Production of thin praseodymium (Pr) oxide film as dielectric in an electronic element of a semiconductor device comprises depositing, from the gas phase, a chemically reactive Pr compound (I) on (sections of) a substrate surface, and converting this to Pr oxide with a chemically reactive oxygen compound (II) also deposited from the gas phase.

公开(公告)号：DE50207441D1

公开(公告)日：2006-08-17

申请号：DE50207441

申请日：2002-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  HECHT THOMAS

IPC: C23C16/02 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: The invention relates to a method for production of a metallic or metal-containing layer ( 5 ) by using a pre-cursor on a silicon- or germanium-containing layer, of, in particular, an electronic component, whereby an intermediate layer is applied to the silicon- or germanium-containing layer before the use of the pre-cursor. Said intermediate layer forms a diffusion barrier for at least those elements or the pre-cursor which would etch the silicon- or germanium-containing layer and is itself resistant to etching by the pre-cursor.

公开(公告)号：DE10211932B9

公开(公告)日：2006-03-30

申请号：DE10211932

申请日：2002-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS

IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/00 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50 ,  H03F3/195

Abstract: A circuit arrangement includes a bit line ( 10 ), a reference bit line ( 12 ), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor ( 20, 22 ) and a p-channel field-effect transistor ( 30, 32 ), and also, at the respective source terminals, two voltage sources ( 40, 42 ), of which the voltage source ( 40 ) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source ( 42 ) linked to the p-channel field-effect transistors ( 30, 32 ) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell ( 4 ) on the bit line ( 10 ) if the threshold voltages (U TH1 , U TH2 ) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell ( 4 ).