公开(公告)号：JP2006295196A

公开(公告)日：2006-10-26

申请号：JP2006111855

申请日：2006-04-14

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： AVELLAN ALEJANDRO ,  HECHT THOMAS ,  JAKSCHIK STEFAN ,  SCHROEDER UWE

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/78

CPC classification number: H01L28/65 ,  H01L27/1087 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an electronic element such as a DRAM semiconductor memory with which proper capacitor characteristics or recording characteristics can be obtained even if the capacitor structure is very small, or a field effect transistor.
SOLUTION: In a method for manufacturing an electronic element in which a dielectric (130) and at least one capacitor (150) having at least one connection electrode (120, 140) are formed, particularly, a DRAM semiconductor memory or a field effect transistor, in order to create a capacitor to obtain optimum capacitor characteristics even if the capacitor structure is very small, the dielectric (130) or the connection electrode (120, 140) is formed such that the occurrence of transient polarization is suppressed or at least reduced.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于制造诸如DRAM半导体存储器的电子元件的方法，即使电容器结构非常小也能够获得适当的电容器特性或记录特性，或场效应晶体管。 解决方案：在制造其中形成电介质（130）和至少一个具有至少一个连接电极（120,140）的电容器（150）的电子元件的方法中，特别地，DRAM半导体存储器或 场效应晶体管，为了形成电容器以获得最佳的电容器特性，即使电容器结构非常小，电介质（130）或连接电极（120,140）形成为使得瞬态极化的发生被抑制或 至少减少 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO02067330A3

公开(公告)日：2003-03-20

申请号：PCT/EP0201800

申请日：2002-02-20

Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH MATTHIAS ,  HECHT THOMAS

Inventor： GOLDBACH MATTHIAS ,  HECHT THOMAS

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10861 ,  H01L27/10867

Abstract: The invention relates to an electrode arrangement for charge storage with an external trench electrode (202; 406), embodied along the wall of a trench provided in a substrate (401) and electrically insulated on both sides in the trench by a first and a second dielectric (104; 405, 409); an internal trench electrode (201; 410), serving as counter-electrode to the external trench electrode (201; 406) and insulated by the second dielectric (104; 409) and a substrate electrode (201; 403), which is insulated by the first dielectric (104; 405) outside the trench, which serves as counter-electrode to the external trench electrode (202; 406) and is connected to the internal trench electrode (201; 410) in the upper trench region.

Abstract translation: 本发明提供电极装置，用于存储具有外严重电极（202; 406）的电荷（; 405，409 104）电隔离的由第一和第二电介质沿着形成在沟槽的衬底（401）的壁，并且在两侧上的沟槽提供 是; 由第二介电层（409 104）;在所述沟槽隔离;内严重电极（410 201）用作反电极与外部电极严重（406 201）; 连接，和衬底电极（201; 403），该绝缘沟槽的外侧从所述第一电介质（104; 405）;;中使用并与内严重电极作为对电极，以所述外严重电极（406 202）（410 201）上严重的区域。

公开(公告)号：WO2004031439A3

公开(公告)日：2004-11-04

申请号：PCT/DE0303188

申请日：2003-09-24

Applicant: INFINEON TECHNOLOGIES AG ,  HECHT THOMAS ,  LUETZEN JOERN

Inventor： HECHT THOMAS ,  LUETZEN JOERN

IPC: C23C16/44 ,  C23C16/455

CPC classification number: C23C16/4412 ,  C23C16/45544 ,  C23C16/45557

Abstract: A sequential gas phase deposition (ALD, atomic layer deposition) of two or more precursors, introduced by means of process gases is controlled in a process chamber (10) of a process reactor (1), whereby the process chamber (10) is connected to an auxiliary chamber (20) for a precursor change and the precursor to be removed is thus diluted in the process chamber (10), such that a process duration in the sequential gas phase deposition, as determined by a precursor exchange, is shortened.

公开(公告)号：WO03017342A2

公开(公告)日：2003-02-27

申请号：PCT/DE0202651

申请日：2002-07-18

Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH MATTHIAS ,  HECHT THOMAS ,  LUETZEN JOERN ,  SELL BERNHARD

Inventor： GOLDBACH MATTHIAS ,  HECHT THOMAS ,  LUETZEN JOERN ,  SELL BERNHARD

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L27/10867 ,  H01L21/0274

Abstract: A structure on a layer surface of the semiconductor wafer comprises at least one first surface (8,9) area reflecting electromagnetic radiation and at least one second substantially non-reflecting surface area (10,11,12). A transparent insulating layer (13) and a light-sensitive layer are produced on said layer surface. Electromagnetic radiation is directed at the light-sensitive layer at an incident angle &thetas; and the structure of the layer surface is imaged onto the light-sensitive layer with a lateral replacement.

Abstract translation: 在半导体晶片的表面层的结构具有至少一个反射电磁辐射的第一区域（8,9）和至少一个第二基本上非反射区域的区域（10,11,12）。 在该表面层的透明绝缘层（13）和一光敏层被产生。 的电磁辐射是在入射角θ驱动＆; 引导到感光层，并准备在层表面的结构与在感光层中的横向更换。

公开(公告)号：DE102005057255B4

公开(公告)日：2007-09-20

申请号：DE102005057255

申请日：2005-12-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERNHARDT HENRY ,  HECHT THOMAS ,  STADTMUELLER MICHAEL ,  KIM YEONG KWAN ,  KAPTEYN CHRISTIAN ,  SCHROEDER UWE ,  SPITZER ANDREAS

IPC: H01L27/108 ,  H01L21/8242

Abstract: The capacitor has a first electrode layer (103), a second electrode layer (104,105) and a dielectric intermediate layer (110) between the electrode layers. The dielectric layer contains a high k dielectric and at least one component containing silicon. Independent claims also cover a method of manufacture.

公开(公告)号：DE102004028030B4

公开(公告)日：2006-07-27

申请号：DE102004028030

申请日：2004-06-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKSCHIK STEFAN ,  SCHROEDER UWE ,  HECHT THOMAS

IPC: H01L21/314 ,  C23C14/04 ,  C23C16/02 ,  C23C16/04 ,  C23C16/40 ,  H01L21/20 ,  H01L21/283 ,  H01L21/285 ,  H01L21/31 ,  H01L21/44 ,  H01L21/469 ,  H01L21/66 ,  H01L21/762 ,  H01L21/768

Abstract: The present invention provides a coating process for patterned substrate surfaces, in which a substrate ( 101 ) is provided, the substrate having a surface ( 105 ) which is patterned in a substrate patterning region ( 102 ) and has one or more trenches ( 106 ) that are to be filled to a predetermined filling height ( 205 ), a catalyst layer ( 201 ) is introduced into the trenches ( 106 ) that are to be filled, a reaction layer ( 202 ) is deposited catalytically in the trenches ( 106 ) that are to be filled, the catalytically deposited reaction layer ( 202 ) is densified in the trenches ( 106 ) that are to be filled, and the introduction of the catalyst layer ( 201 ) and the catalytic deposition of the reaction layer ( 202 ) are repeated until the trenches ( 106 ) that are to be filled have been filled to the predetermined filling height ( 205 ).

公开(公告)号：DE10147120B4

公开(公告)日：2005-08-25

申请号：DE10147120

申请日：2001-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  HECHT THOMAS

IPC: H01L21/8242 ,  H01L27/108

Abstract: A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.

公开(公告)号：DE10357756A1

公开(公告)日：2005-07-14

申请号：DE10357756

申请日：2003-12-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  SCHROEDER UWE ,  JAKSCHIK STEFAN

IPC: C23C16/30 ,  C23C16/455 ,  H01L21/314 ,  H01L21/8242 ,  C23C16/00

Abstract: Production of metal oxynitride layers comprises depositing a chemically reactive metal compound on the surface of a substrate in the gas phase and reacting with nitrogen oxide and/or dinitrogen monoxide. The metal oxynitride is not silicon oxynitride (SiON). An independent claim is also included for a metal oxynitride layer produced by the above process.

公开(公告)号：DE10359580B3

公开(公告)日：2005-06-30

申请号：DE10359580

申请日：2003-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SESTERHENN MICHAEL ,  SCHLOESSER TILL ,  HECHT THOMAS

IPC: H01L21/265 ,  H01L21/76 ,  H01L21/8242

Abstract: The present invention provides a fabrication method for a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact. After forming and sinking an electrically conductive filling, an insulation collar and, if appropriate, a buried contact that is connected on all sides, the following are effected: providing at least one liner layer in the trench; filling the trench with a filling made of an auxiliary material, which filling is encapsulated by the at least one liner layer in the trench; providing a mask on the filling for defining the structure of the buried contact, the mask having no projections into the trench; removing a part of the filling using the mask; removing an underlying part of the at least one liner layer for uncovering a corresponding part of the insulation collar.

公开(公告)号：DE10234735A1

公开(公告)日：2004-02-12

申请号：DE10234735

申请日：2002-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  GOLDBACH MATTHIAS ,  SCHROEDER UWE

IPC: C23C16/04 ,  C23C16/44 ,  C23C16/455 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/314 ,  H01L21/334 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: Structurization of process area (2) of substrate (1) with relief, inclined and/or perpendicular to horizontal substrate surface (101) and extending into relief to given coating depth (102) between relief depth (103) and substrate surface, involves depositing liner (3) from precursors in process chamber; limited deposition of at least one precursor and coating in uniform thickness almost only on upper part between substrate surface and coating depth.