公开(公告)号：EP2812795A4

公开(公告)日：2015-10-21

申请号：EP12868166

申请日：2012-02-07

Applicant: INTEL CORP

Inventor： ROBENKO ALEXANDER ,  ANDERSON ANDREW

IPC: G06F9/455 ,  G06F12/10

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F12/1009 ,  G06F2009/45583

Abstract: In one embodiment, a method includes creating a first working set of shadow page table hierarchies for a first processor of a plurality of processors, creating a second working set of shadow page table hierarchies for a second processor of the plurality of processors, keeping a record of modified guest page tables, and synchronizing each modified guest page table with a corresponding shadow page table in the first working set. For each modified guest page table in the modified guest page tables record, an entry includes an indication of which of the plurality of processors have a hardware translation lookaside buffer containing a writable reference to the modified guest page table.

Abstract translation: 在一个，实施例的方法包括用于处理器的多个第一处理器创建影子页表分层结构的第一工作组，创建第二工作集影子页表分层结构的用于处理器的多个第二处理器，保持记录 修改的客户页表的，和同步与在第一工作组对应的影子页表中的每个修改的客户页面表。 对于修改的客户页面表记录每个修改的客户页面表，一个条目包括在处理器的多个哪家的指示有一个硬件转换后备缓冲器包含一个可写参考修改的客户页面表。

公开(公告)号：DE112004003066B4

公开(公告)日：2016-07-28

申请号：DE112004003066

申请日：2004-09-10

Applicant: INTEL CORP

Inventor： NEIGER GILBERT ,  BENNETT STEVEN ,  KAGI ALAIN ,  JEYASINGH STALINSELVARAJ ,  ANDERSON ANDREW ,  UHLIG RICHARD ,  COTA-ROBLES ERIK ,  RODGERS SCOTT ,  SMITH III LAWRENCE

IPC: G06F9/46 ,  G06F9/455

Abstract: Prozessor mit einer Leitwegelogik in Form eines Mikrocodes, einer programmierbaren Logik oder einer hartcodierten Logik, wobei die Leitwegelogik ausgebildet ist, das folgende Verfahren auf dem Prozessor auszuführen, wenn darauf mehrere Virtual Machine Monitore parallel eingerichtet sind: Erkennen des Auftretens eines privilegierten Ereignisses während des Betriebs von Gast-Software auf einer virtuellen Maschine (VM) oder während des Betriebs eines Virtual Machine Monitors, wobei privilegierte Ereignisse von der Gast-Software nicht behandelt werden können und die mehreren Virtual Machine Monitore eingerichtet sind, privilegierte Ereignisse zu behandeln; Ermitteln des Typs des erkannten privilegierten Ereignisses; Ermitteln eines Wertes aus einem Prozessor-Register oder einem Speicher im Plattform-Chipsatz, das bzw. der mit dem Typ des privilegierten Ereignisses verbunden ist; Identifizieren eines der eingerichteten Virtual Machine Monitore durch den ermittelten Wert, um das erkannte privilegierte Ereignis durch den identifizierten Virtual Machine Monitor zu behandeln; Leiten des erkannten privilegierten Ereignisses zum identifizierten Virtual Machine Monitor; Erzeugen eines VM-Exit Befehls, um die Steuerung von der aktuell ausgeführten Gast-Software beziehungsweise dem aktuell ausgeführten Virtual Maschine Monitor auf den identifizierten Virtual Machine Monitor zu übertragen.

公开(公告)号：BRPI0715394A2

公开(公告)日：2013-06-25

申请号：BRPI0715394

申请日：2007-08-06

Applicant: INTEL CORP

Inventor： COTA-ROBLES ERIK ,  NEIGER GILBERT ,  BENNETT STEVEN ,  ANDERSON ANDREW

IPC: G06F9/06 ,  G06F9/54

Abstract: Embodiments of apparatuses, methods, and systems for virtualizing performance counters are disclosed. In one embodiment, an apparatus includes a counter, a counter enable storage location, counter enable logic, and virtual machine control logic. The counter enable storage location is to store a counter enable indicator. The counter enable logic is to enable the counter based on the counter enable indicator. The virtual machine control logic is to transfer control of the apparatus to a guest. The virtual machine control logic includes guest state load logic to cause a guest value from a virtual machine control structure to be loaded into the counter enable storage location in connection with a transfer of control of the apparatus to the guest.

公开(公告)号：DE112005002360T5

公开(公告)日：2007-08-23

申请号：DE112005002360

申请日：2005-09-21

Applicant: INTEL CORP

Inventor： NEIGER GILBERT ,  BENNETT STEVEN ,  COTA-ROBLES ERIK ,  SCHOENBERG SEBASTIAN ,  HALL CLIFFORD ,  RODGERS DION ,  SMITH LAWRENCE ,  ANDERSON ANDREW ,  UHLIG RICHARD ,  KOZUCH MICHAEL ,  GLEW ANDY

IPC: G06F9/455

Abstract: In one embodiment, a method includes transitioning control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a VMM timer indicator is set to an enabling value, and identifying a VMM timer value configured by the VMM. The method further includes periodically comparing a current value of a timing source with the VMM timer value, generating an internal event if the current value of the timing source has reached the VMM timer value, and transitioning control to the VMM in response to the internal event without incurring an event handling procedure in any one of the VMM and the VM.

公开(公告)号：AU2003245543A8

公开(公告)日：2004-01-19

申请号：AU2003245543

申请日：2003-06-19

Applicant: INTEL CORP

Inventor： JEYASINGH STALINSELVARAJ ,  BENNETT STEVEN ,  UHLIG RICHARD ,  NEIGER GILBERT ,  KAGI ALAIN ,  ANDERSON ANDREW ,  COTA-ROBLES ERIK

IPC: G06F11/07 ,  G06F9/44

Abstract: In one embodiment, fault information relating to a fault associated with the operation of guest software is received. Further, a determination is made as to whether the fault information satisfies one or more fault filtering criteria. If the determination is positive, the guest software is permitted to disregard the fault.

公开(公告)号：PL3572937T3

公开(公告)日：2022-04-04

申请号：PL19160715

申请日：2006-01-10

Applicant: INTEL CORP

Inventor： BENNETT STEVEN ,  ANDERSON ANDREW ,  NEIGER GILBERT ,  SANKARAN RAJESH ,  SMITH LARRY ,  UHLIG RICHARD ,  RODGERS DION

IPC: G06F12/109 ,  G06F9/455

公开(公告)号：DE112006001642T5

公开(公告)日：2008-05-08

申请号：DE112006001642

申请日：2006-06-20

Applicant: INTEL CORP

Inventor： SANKARAN RAJESH ,  STEINBERG UDO ,  BENNETT STEVEN ,  ANDERSON ANDREW ,  NEIGER GILBERT

IPC: G06F13/28 ,  G06F12/10

Abstract: An apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit of the apparatus includes a translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations.

公开(公告)号：GB2420889B

公开(公告)日：2007-04-25

申请号：GB0602500

申请日：2004-09-10

Applicant: INTEL CORP

Inventor： NEIGER GILBERT ,  BENNETT STEVEN ,  KAGI ALAIN ,  JEYASINGH STALINSELVARAJ ,  ANDERSON ANDREW ,  UHLIG RICHARD ,  COTA-ROBLES ERIK ,  RODGERS SCOTT ,  SMITH LAWRENCE III

IPC: G06F9/455 ,  G06F9/46

公开(公告)号：DE112004001697T5

公开(公告)日：2006-07-13

申请号：DE112004001697

申请日：2004-09-10

Applicant: INTEL CORP

Inventor： NEIGER GILBERT ,  BENNETT STEVEN ,  KAGI ALAIN ,  JEYASINGH STALINSELVARAJ ,  ANDERSON ANDREW ,  UHLIG RICHARD ,  COTA-ROBLES ERIK ,  RODGERS SCOTT ,  SMITH III LAWRENCE

IPC: G06F9/455

公开(公告)号：GB2420207A

公开(公告)日：2006-05-17

申请号：GB0603362

申请日：2004-09-15

Applicant: INTEL CORP

Inventor： BENNETT STEPHEN ,  ANDERSON ANDREW ,  JEYASINGH STALINSELVARAJ ,  KAGI ALAIN ,  NEIGER GILBERT ,  UHLIG RICHARD ,  KOZUCH MICHAEL ,  SMITH LAWRENCE III ,  RODGERS SCOTT

IPC: G06F9/455

Abstract: In one embodiment, a request to transition control to a virtual machine (VM) is received from a virtual machine monitor (VMM) and a determination is made as to whether the VMM has requested a delivery of a fault to the VM. If the determination is positive, the fault is delivered to the VM when control is transitioned to the VM.