公开(公告)号：EP2588958A4

公开(公告)日：2016-11-02

申请号：EP11804047

申请日：2011-06-22

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG C ,  BRETERNITZ MAURICIO JR ,  LIU WEI

IPC: G06F9/46 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/30076 ,  G06F9/30174 ,  G06F9/3879 ,  G06F9/4893 ,  Y02D10/24

Abstract: An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co-designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.

公开(公告)号：EP2684127A4

公开(公告)日：2014-11-26

申请号：EP11860992

申请日：2011-12-28

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG

IPC: G06F9/48 ,  G06F9/44 ,  G06F15/80

CPC classification number: G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：AU2011280088B2

公开(公告)日：2015-01-22

申请号：AU2011280088

申请日：2011-06-27

Applicant: INTEL CORP

Inventor： BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  BONE NIR ,  AVNI SHLOMO

IPC: G06F9/06 ,  G06F9/30

Abstract: Methods and apparatus relating to accelerating execution of compressed code are described. In one embodiment, a two-level embedded code decompression scheme is utilized which eliminates bubbles, which may increase speed and/or reduce power consumption. Other embodiments are also described and claimed.

公开(公告)号：SG188993A1

公开(公告)日：2013-05-31

申请号：SG2013018742

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：EP2619654A4

公开(公告)日：2016-11-16

申请号：EP11827728

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

IPC: G06F9/45 ,  G06F9/06 ,  G06F9/30 ,  G06F9/305 ,  G06F15/76

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 的装置和方法被描述为有条件地提交和/或推测检查点的交易，这潜在地导致了交易的动态调整。 在二进制代码动态优化，交易被插入到内存提供保障顺序，使动态优化，以更积极的优化代码。 和条件提交启用动态优化代码的执行效率，同时努力避免用尽硬件资源的交易。 虽然投机性的检查站时能交易的中止快速高效的恢复。 处理器硬件angepasst支持交易的动态调整，为寻求包括解码器确实承认条件提交指令，推测检查点指令，或两者兼而有之。 和处理器的硬件是执行操作，以支持条件提交或推测检查点的响应于解码请示此外angepasst。

公开(公告)号：EP2585907A4

公开(公告)日：2016-05-25

申请号：EP11810085

申请日：2011-06-27

Applicant: INTEL CORP

Inventor： BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  BONE NIR ,  AVNI SHLOMO

IPC: G06F9/30

CPC classification number: H03M7/30 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/382 ,  G06F9/445 ,  Y02D10/43

Abstract: Methods and apparatus relating to accelerating execution of compressed code are described. In one embodiment, a two-level embedded code decompression scheme is utilized which eliminates bubbles, which may increase speed and/or reduce power consumption. Other embodiments are also described and claimed.

Abstract translation: 描述与加速执行压缩代码相关的方法和装置。 在一个实施例中，利用消除气泡的两级嵌入式代码解压缩方案，这可以增加速度和/或降低功耗。 还描述和要求保护其他实施例。

公开(公告)号：EP2619655A4

公开(公告)日：2015-03-04

申请号：EP11827755

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/30 ,  G06F9/06 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F9/3842 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3857