公开(公告)号：AU2011280088A1

公开(公告)日：2013-01-24

申请号：AU2011280088

申请日：2011-06-27

Applicant: INTEL CORP

Inventor： BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  BONE NIR ,  AVNI SHLOMO

IPC: G06F9/06 ,  G06F9/30

Abstract: Methods and apparatus relating to accelerating execution of compressed code are described. In one embodiment, a two-level embedded code decompression scheme is utilized which eliminates bubbles, which may increase speed and/or reduce power consumption. Other embodiments are also described and claimed.

公开(公告)号：AU2011305091A1

公开(公告)日：2013-03-14

申请号：AU2011305091

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/06 ,  G06F9/30

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：WO2012040742A3

公开(公告)日：2012-06-14

申请号：PCT/US2011053337

申请日：2011-09-26

Applicant: INTEL CORP ,  WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/30 ,  G06F9/06

CPC classification number: G06F9/3842 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3857

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 本文描述了用于有条件地提交/推测的检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时试图阻止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

公开(公告)号：AU2011305091B2

公开(公告)日：2014-09-25

申请号：AU2011305091

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/06 ,  G06F9/30

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：WO2012040715A3

公开(公告)日：2012-06-21

申请号：PCT/US2011053285

申请日：2011-09-26

Applicant: INTEL CORP ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

Inventor： BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

IPC: G06F9/30 ,  G06F9/06 ,  G06F9/305 ,  G06F15/76

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 本文描述了用于有条件地提交/推测的检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。 虽然投机检查点可以在交易中止时快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

公开(公告)号：WO2012012112A3

公开(公告)日：2012-04-05

申请号：PCT/US2011041967

申请日：2011-06-27

Applicant: INTEL CORP ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  BONE NIR ,  AVNI SHLOMO

Inventor： BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  BONE NIR ,  AVNI SHLOMO

IPC: G06F9/30 ,  G06F9/06

CPC classification number: H03M7/30 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/382 ,  G06F9/445 ,  Y02D10/43

Abstract: Methods and apparatus relating to accelerating execution of compressed code are described. In one embodiment, a two-level embedded code decompression scheme is utilized which eliminates bubbles, which may increase speed and/or reduce power consumption. Other embodiments are also described and claimed.

Abstract translation: 描述与加速压缩代码执行有关的方法和装置。 在一个实施例中，利用消除气泡的两级嵌入式代码解压缩方案，这可以增加速度和/或降低功耗。 还描述和要求保护其他实施例。

公开(公告)号：AU2011280088B2

公开(公告)日：2015-01-22

申请号：AU2011280088

申请日：2011-06-27

Applicant: INTEL CORP

Inventor： BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  BONE NIR ,  AVNI SHLOMO

IPC: G06F9/06 ,  G06F9/30

Abstract: Methods and apparatus relating to accelerating execution of compressed code are described. In one embodiment, a two-level embedded code decompression scheme is utilized which eliminates bubbles, which may increase speed and/or reduce power consumption. Other embodiments are also described and claimed.

公开(公告)号：SG188993A1

公开(公告)日：2013-05-31

申请号：SG2013018742

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：EP2619654A4

公开(公告)日：2016-11-16

申请号：EP11827728

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

IPC: G06F9/45 ,  G06F9/06 ,  G06F9/30 ,  G06F9/305 ,  G06F15/76

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 的装置和方法被描述为有条件地提交和/或推测检查点的交易，这潜在地导致了交易的动态调整。 在二进制代码动态优化，交易被插入到内存提供保障顺序，使动态优化，以更积极的优化代码。 和条件提交启用动态优化代码的执行效率，同时努力避免用尽硬件资源的交易。 虽然投机性的检查站时能交易的中止快速高效的恢复。 处理器硬件angepasst支持交易的动态调整，为寻求包括解码器确实承认条件提交指令，推测检查点指令，或两者兼而有之。 和处理器的硬件是执行操作，以支持条件提交或推测检查点的响应于解码请示此外angepasst。

公开(公告)号：EP2585907A4

公开(公告)日：2016-05-25

申请号：EP11810085

申请日：2011-06-27

Applicant: INTEL CORP

Inventor： BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  BONE NIR ,  AVNI SHLOMO

IPC: G06F9/30

CPC classification number: H03M7/30 ,  G06F9/30145 ,  G06F9/30178 ,  G06F9/382 ,  G06F9/445 ,  Y02D10/43

Abstract: Methods and apparatus relating to accelerating execution of compressed code are described. In one embodiment, a two-level embedded code decompression scheme is utilized which eliminates bubbles, which may increase speed and/or reduce power consumption. Other embodiments are also described and claimed.

Abstract translation: 描述与加速执行压缩代码相关的方法和装置。 在一个实施例中，利用消除气泡的两级嵌入式代码解压缩方案，这可以增加速度和/或降低功耗。 还描述和要求保护其他实施例。