公开(公告)号：WO2012040742A3

公开(公告)日：2012-06-14

申请号：PCT/US2011053337

申请日：2011-09-26

Applicant: INTEL CORP ,  WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/30 ,  G06F9/06

CPC classification number: G06F9/3842 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3857

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 本文描述了用于有条件地提交/推测的检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时试图阻止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

公开(公告)号：WO2012125200A3

公开(公告)日：2012-11-15

申请号：PCT/US2011067630

申请日：2011-12-28

Applicant: INTEL CORP ,  WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG

Inventor： WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG

IPC: G06F9/48 ,  G06F9/44 ,  G06F15/80

CPC classification number: G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Abstract translation: 在异构多核处理系统上动态切换核可以通过在第一处理核上执行程序代码来执行。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能度量比先前确定的核心性能度量好时，可以用信号通知第二处理核心的掉电，并且程序代码的执行可以在第一处理核心上继续。 当第一性能度量不比先前确定的核心性能度量好时，可以将程序代码的执行从第一处理核心切换到第二处理核心。

公开(公告)号：WO2012040715A3

公开(公告)日：2012-06-21

申请号：PCT/US2011053285

申请日：2011-09-26

Applicant: INTEL CORP ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

Inventor： BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

IPC: G06F9/30 ,  G06F9/06 ,  G06F9/305 ,  G06F15/76

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 本文描述了用于有条件地提交/推测的检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。 虽然投机检查点可以在交易中止时快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

公开(公告)号：WO2011056278A3

公开(公告)日：2011-06-30

申请号：PCT/US2010046685

申请日：2010-08-25

Applicant: INTEL CORP ,  BLOMSTEDT JOSEPH ,  WANG CHENG ,  WU YOUFENG

Inventor： BLOMSTEDT JOSEPH ,  WANG CHENG ,  WU YOUFENG

IPC: G06F17/21 ,  G06F9/30 ,  G06F9/38 ,  G06F13/14

CPC classification number: G06F11/3604 ,  G06F8/433 ,  G06F8/456

Abstract: In one embodiment of the invention a method comprising (1) receiving an unstructured binary code region that is single-threaded; (2) determining a slice criterion for the region; (3) determining a call edge, a return edge, and a fallthrough pseudo-edge for the region based on analysis of the region at a binary level; and (4) determining a context-sensitive slice based on the call edge, the return edge, the fallthrough pseudo-edge, and the slice criterion. Embodiments of the invention may include a program analysis technique that can be used to provide context-sensitive slicing of binary programs for slicing hot regions identified at runtime, with few underlying assumptions about the program from which the binary is derived. Also, in an embodiment a slicing method may include determining a context-insensitive slice, when a time limit is met, by determining the context-insensitive slice while treating call edges as a normal control flow edges.

Abstract translation: 在本发明的一个实施例中，一种方法包括：（1）接收单线程的非结构化二进制码区; （2）确定该区域的切片标准; （3）基于二进制级别的区域分析来确定区域的呼叫边缘，返回边缘和穿透式伪边缘; （4）基于呼叫边缘，返回边缘，下穿伪边缘和切片标准来确定上下文敏感切片。 本发明的实施例可以包括程序分析技术，该程序分析技术可以用于提供用于对在运行时识别的热区域进行切片的二进制程序的上下文敏感的分片，而关于从其导出二进制的程序的基本假设很少。 而且，在一个实施例中，切片方法可以包括当满足时间限制时确定上下文不敏感切片，通过确定上下文不敏感切片而将呼叫边缘视为正常控制流边缘。

公开(公告)号：EP3234766A4

公开(公告)日：2018-07-04

申请号：EP15870562

申请日：2015-11-16

Applicant: INTEL CORP

Inventor： WANG CHENG ,  WU YOUFENG ,  BAGHSORKHI SARA S ,  HARTONO ALBERT ,  VALENTINE ROBERT

IPC: G06F9/30 ,  G06F8/41 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/528 ,  G06F8/41 ,  G06F8/4451 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F12/0828 ,  G06F12/0875 ,  G06F2212/452

Abstract: Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.

公开(公告)号：EP3123341A4

公开(公告)日：2017-10-25

申请号：EP15769489

申请日：2015-03-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  WU YOUFENG ,  RONG HONGBO ,  PARK HYUNCHUL

IPC: G06F13/10 ,  G06F9/44 ,  G06F9/455

CPC classification number: G06F9/45516 ,  G06F9/4411 ,  G06F9/4552 ,  G06F13/10

Abstract: In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.

公开(公告)号：EP2695061A4

公开(公告)日：2017-05-17

申请号：EP11863199

申请日：2011-11-29

Applicant: INTEL CORP

Inventor： WANG CHENG ,  WU YOUFENG

IPC: G06F9/50 ,  G06F9/06 ,  G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3838 ,  G06F9/384

公开(公告)号：EP2619654A4

公开(公告)日：2016-11-16

申请号：EP11827728

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

IPC: G06F9/45 ,  G06F9/06 ,  G06F9/30 ,  G06F9/305 ,  G06F15/76

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 的装置和方法被描述为有条件地提交和/或推测检查点的交易，这潜在地导致了交易的动态调整。 在二进制代码动态优化，交易被插入到内存提供保障顺序，使动态优化，以更积极的优化代码。 和条件提交启用动态优化代码的执行效率，同时努力避免用尽硬件资源的交易。 虽然投机性的检查站时能交易的中止快速高效的恢复。 处理器硬件angepasst支持交易的动态调整，为寻求包括解码器确实承认条件提交指令，推测检查点指令，或两者兼而有之。 和处理器的硬件是执行操作，以支持条件提交或推测检查点的响应于解码请示此外angepasst。

公开(公告)号：EP2619655A4

公开(公告)日：2015-03-04

申请号：EP11827755

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/30 ,  G06F9/06 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F9/3842 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3857

公开(公告)号：EP2494468A4

公开(公告)日：2013-11-20

申请号：EP10828698

申请日：2010-08-25

Applicant: INTEL CORP

Inventor： BLOMSTEDT JOSEPH ,  WANG CHENG ,  WU YOUFENG

IPC: G06F17/21 ,  G06F9/30 ,  G06F9/38 ,  G06F9/45 ,  G06F11/36 ,  G06F13/14

CPC classification number: G06F11/3604 ,  G06F8/433 ,  G06F8/456

Abstract: In one embodiment of the invention a method comprising (1) receiving an unstructured binary code region that is single-threaded; (2) determining a slice criterion for the region; (3) determining a call edge, a return edge, and a fallthrough pseudo-edge for the region based on analysis of the region at a binary level; and (4) determining a context-sensitive slice based on the call edge, the return edge, the fallthrough pseudo-edge, and the slice criterion. Embodiments of the invention may include a program analysis technique that can be used to provide context-sensitive slicing of binary programs for slicing hot regions identified at runtime, with few underlying assumptions about the program from which the binary is derived. Also, in an embodiment a slicing method may include determining a context-insensitive slice, when a time limit is met, by determining the context-insensitive slice while treating call edges as a normal control flow edges.