公开(公告)号：JP2011129103A

公开(公告)日：2011-06-30

申请号：JP2010248263

申请日：2010-11-05

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LIU WEI ,  WU YOUFENG ,  WILKERSON CHRISTOPHER B ,  HUM HERBERT H

IPC: G06F12/08 ,  G06F9/45

CPC classification number: G06F12/0888 ,  G06F8/4442 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/383 ,  Y02B60/1225 ,  Y02D10/13

Abstract: PROBLEM TO BE SOLVED: To provide a method and apparatus for power and time efficient load handling. SOLUTION: A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供用于功率和时间有效的负载处理的方法和装置。 解决方案：编译器可以识别生产者负载，消费者重用负载，消费者转发负载以及生产者/消费者混合负载。 基于该识别，可以将负载的性能有效地指向负载值缓冲器，存储缓冲器，数据高速缓存或其他位置。 因此，通过从负载值缓冲区和存储缓冲区的直接加载，减少对高速缓存的访问，从而有效地处理负载。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2012040742A3

公开(公告)日：2012-06-14

申请号：PCT/US2011053337

申请日：2011-09-26

Applicant: INTEL CORP ,  WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/30 ,  G06F9/06

CPC classification number: G06F9/3842 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3857

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 本文描述了用于有条件地提交/推测的检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时试图阻止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

公开(公告)号：WO2012005949A3

公开(公告)日：2012-05-18

申请号：PCT/US2011041429

申请日：2011-06-22

Applicant: INTEL CORP ,  WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG C ,  BRETERNITZ MAURICIO JR ,  LIU WEI

Inventor： WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG C ,  BRETERNITZ MAURICIO JR ,  LIU WEI

IPC: G06F9/46 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F9/30076 ,  G06F9/30174 ,  G06F9/3879 ,  G06F9/4893 ,  Y02D10/24

Abstract: An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co- designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.

Abstract translation: 本文描述了一种用于将第一类型的处理器核与第二类型的共同设计的核耦合的装置和方法。 对第一个核心上的程序代码执行进行监控，并且识别程序代码的热部分。 这些热段在协同设计的核心上进行优化，以便随后遇到这些热部分，优化的热段在协同设计的核心上执行。 当共同设计的核心正在执行优化的热代码时，第一处理器核心可以处于低功率状态以节省功率或并行执行其他代码。 此外，多个冷码线程可以在第一核心上流水线化，而多个热代码线程在共同设计的核心上进行流水线以实现最大性能。

公开(公告)号：WO2012006030A2

公开(公告)日：2012-01-12

申请号：PCT/US2011042040

申请日：2011-06-27

Applicant: INTEL CORP ,  LIU WEI ,  WU YOUFENG

Inventor： LIU WEI ,  WU YOUFENG

IPC: G06F9/46 ,  G06F9/06 ,  G06F9/30

CPC classification number: G06F9/3834 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/52

Abstract: In one embodiment, the present invention introduces a speculation engine to parallelize serial instructions by creating separate threads from the serial instructions and inserting processor instructions to set a synchronization bit before a dependence source and to clear the synchronization bit after a dependence source, where the synchronization bit is designed to stall a dependence sink from a thread running on a separate core. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明引入了一种推测引擎，以通过从串行指令中创建单独的线程并插入处理器指令来在依赖源之前设置同步位并在依赖源之后清除同步位，从而并行化串行指令，其中同步 位被设计为从在单独核心上运行的线程停止依赖宿。 描述和要求保护其他实施例。

公开(公告)号：EP2588958A4

公开(公告)日：2016-11-02

申请号：EP11804047

申请日：2011-06-22

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG C ,  BRETERNITZ MAURICIO JR ,  LIU WEI

IPC: G06F9/46 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/30076 ,  G06F9/30174 ,  G06F9/3879 ,  G06F9/4893 ,  Y02D10/24

Abstract: An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co-designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.

公开(公告)号：EP2588959A4

公开(公告)日：2014-04-16

申请号：EP11804093

申请日：2011-06-27

Applicant: INTEL CORP

Inventor： LIU WEI ,  WU YOUFENG

IPC: G06F9/46 ,  G06F9/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/3834 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/52

公开(公告)号：EP2619655A4

公开(公告)日：2015-03-04

申请号：EP11827755

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/30 ,  G06F9/06 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F9/3842 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3857

公开(公告)号：AU2011276588A1

公开(公告)日：2013-01-10

申请号：AU2011276588

申请日：2011-06-27

Applicant: INTEL CORP

Inventor： LIU WEI ,  WU YOUFENG

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/46

Abstract: In one embodiment, the present invention introduces a speculation engine to parallelize serial instructions by creating separate threads from the serial instructions and inserting processor instructions to set a synchronization bit before a dependence source and to clear the synchronization bit after a dependence source, where the synchronization bit is designed to stall a dependence sink from a thread running on a separate core. Other embodiments are described and claimed.

公开(公告)号：AU2011276656B2

公开(公告)日：2015-08-20

申请号：AU2011276656

申请日：2011-06-22

Applicant: INTEL CORP

Inventor： WU YOUFENG ,  HU SHILIANG ,  BORIN EDSON ,  WANG CHENG C ,  BRETERNITZ MAURICIO JR ,  LIU WEI

IPC: G06F1/32 ,  G06F9/38 ,  G06F9/46

Abstract: An apparatus and method is described herein for coupling a processor core of a first type with a co-designed core of a second type. Execution of program code on the first core is monitored and hot sections of the program code are identified. Those hot sections are optimize for execution on the co-designed core, such that upon subsequently encountering those hot sections, the optimized hot sections are executed on the co- designed core. When the co-designed core is executing optimized hot code, the first processor core may be in a low-power state to save power or executing other code in parallel. Furthermore, multiple threads of cold code may be pipelined on the first core, while multiple threads of hot code are pipeline on the co-designed core to achieve maximum performance.

公开(公告)号：AU2011305091A1

公开(公告)日：2013-03-14

申请号：AU2011305091

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/06 ,  G06F9/30

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.