公开(公告)号：EP2972916A4

公开(公告)日：2017-04-12

申请号：EP14778162

申请日：2014-02-26

Applicant: INTEL CORP

Inventor： ROYER JR ROBERT J ,  FANNING BLAISE ,  OOI ENG HUN

IPC: G06F13/14 ,  G06F11/10 ,  G06F12/00

CPC classification number: G06F11/1064 ,  G06F11/1048 ,  G06F12/084 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/313

Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

公开(公告)号：DE112011106078B4

公开(公告)日：2021-01-28

申请号：DE112011106078

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： FANNING BLAISE ,  QAWAMI SHEKOUFEH ,  TETRICK RAYMOND S ,  HADY FRANK T

IPC: G06F12/00 ,  G11C13/02 ,  G11C16/00

Abstract: Verfahren, umfassend:Zuordnen einer ersten Menge (600) eines nicht flüchtigen Direktzugriffsspeichers, NVRAM, (200; 302; 1520) in einem Computersystem, der als Arbeitsspeicher alternativ zu einem dynamischen Direktzugriffsspeicher, DRAM, (114; 300) verwendet wird;Zuordnen einer zweiten Menge (602) des NVRAM (200; 302; 1520), der als Datenspeicher alternativ zu einer Massendatenspeichervorrichtung verwendet wird;während des Betriebs des Computersystems, erneutes Zuordnen mindestens eines ersten Abschnitts der ersten NVRAM-Menge (600) aus der alternativen Arbeitsspeicherzuordnung zur alternativen Datenspeicherzuordnung; undwährend des Betriebs des Computersystems, erneutes Zuordnen mindestens eines ersten Abschnitts der zweiten NVRAM-Menge (602) aus der alternativen Datenspeicherzuordnung zur alternativen Arbeitsspeicherzuordnung.

公开(公告)号：DE112017004916T5

公开(公告)日：2019-06-13

申请号：DE112017004916

申请日：2017-08-24

Applicant: INTEL CORP

Inventor： HINTON GLENN J ,  FANNING BLAISE ,  ALAMELDEEN ALAA R ,  GREENSKY JAMES J

IPC: G06F12/0802

Abstract: Systeme, Vorrichtungen und Verfahren können zum Identifizieren eines ersten Blocks und eines zweiten Blocks bereitgestellt werden, wobei der erste Block eine erste Vielzahl von Cache-Zeilen aufweist, der zweite Block eine zweite Vielzahl von Cache-Zeilen aufweist und der zweite Block sich in einem speicherseitigen Cache befindet. Zusätzlich kann jede Cache-Zeile in der ersten Vielzahl von Cache-Zeilen mit einer entsprechenden Cache-Zeile in der zweiten Vielzahl von Cache-Zeilen komprimiert werden, um einen komprimierten Block zu erhalten, der eine dritte Vielzahl von Cache-Zeilen aufweist. In einem Beispiel wird der zweite Block im speicherseitigen Cache durch den komprimierten Block ersetzt, wenn der komprimierte Block eine Größenbedingung erfüllt.

公开(公告)号：HK1058413A1

公开(公告)日：2004-05-14

申请号：HK04101157

申请日：2004-02-18

Applicant: INTEL CORP

Inventor： FANNING BLAISE

IPC: G06F12/12 ,  G06F

Abstract: An apparatus and a method for optimizing data streaming in a computer system utilizing random access memory in a system logic device have been presented. In one embodiment, the apparatus includes a processor interface unit and a cache to store information received from a processor coupled to the processor interface unit, the cache to store disposable information that may be overwritten without ever having delivered the disposable information to a system memory if the disposable information has been read at least once, the processor interface unit to receive a disposable information attribute indication from the processor when the processor delivers the disposable information to the processor interface unit.

公开(公告)号：AU2002232859A1

公开(公告)日：2002-07-16

申请号：AU2002232859

申请日：2001-12-20

Applicant: INTEL CORP

Inventor： FANNING BLAISE

IPC: G06F12/12 ,  G06F12/08

Abstract: An apparatus and a method for optimizing data streaming in a computer system utilizing random access memory in a system logic device have been presented. In one embodiment, the apparatus includes a processor interface unit and a cache to store information received from a processor coupled to the processor interface unit, the cache to store disposable information that may be overwritten without ever having delivered the disposable information to a system memory if the disposable information has been read at least once, the processor interface unit to receive a disposable information attribute indication from the processor when the processor delivers the disposable information to the processor interface unit.

公开(公告)号：GB2510763A

公开(公告)日：2014-08-13

申请号：GB201408844

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： FANNING BLAISE ,  QAWAMI SHEKOUFEH ,  TETRICK RAYMOND SCOTT ,  HADY FRANK T

IPC: G06F12/02 ,  G06F12/08

Abstract: Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.

公开(公告)号：AT508413T

公开(公告)日：2011-05-15

申请号：AT04815499

申请日：2004-12-23

Applicant: INTEL CORP

Inventor： FANNING BLAISE

IPC: G06F12/08

Abstract: A method and apparatus for a dedicated cache memory are described. Under an embodiment of the invention, a cache memory includes a general-purpose sector and a dedicated sector. The general-purpose sector is to be used for general computer operations. The dedicated sector is to be dedicated to use for a first computer process.

公开(公告)号：DE112007003132T5

公开(公告)日：2009-11-19

申请号：DE112007003132

申请日：2007-12-19

Applicant: INTEL CORP

Inventor： FANNING BLAISE

IPC: G06F13/00 ,  G06F1/26

Abstract: Techniques involving power management techniques in computer systems are disclosed. For instance, an apparatus may include an input output queue (IOQ), an interface coupled to a processor, and a control module. The interface communicates with the processor regarding power states of the processor. The control module may initiate draining the IOQ upon a commencement of a power state transition for the processor. The control module allows the transition of the processor to continue during the draining of the IOQ. However, at a particular point in the transition, the control module may determine whether the IOQ is empty. If so, then the control module may allow the transition of the processor to continue. Otherwise, the control module may stop the transition of the processor until the IOQ is empty.

公开(公告)号：DE60213616T2

公开(公告)日：2007-08-09

申请号：DE60213616

申请日：2002-08-23

Applicant: INTEL CORP

Inventor： AJANOVIC JASMIN ,  HARRIMAN J ,  FANNING BLAISE ,  LEE M

IPC: G06F13/12 ,  G06F3/00 ,  G06F13/00 ,  G06F13/14 ,  G06F13/24 ,  H04L1/18 ,  H04L47/30

Abstract: A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.

公开(公告)号：GB2387697B

公开(公告)日：2005-02-16

申请号：GB0317005

申请日：2001-12-20

Applicant: INTEL CORP

Inventor： FANNING BLAISE

IPC: G06F12/12 ,  G06F12/08

Abstract: An apparatus and a method for optimizing data streaming in a computer system utilizing random access memory in a system logic device have been presented. In one embodiment, the apparatus includes a processor interface unit and a cache to store information received from a processor coupled to the processor interface unit, the cache to store disposable information that may be overwritten without ever having delivered the disposable information to a system memory if the disposable information has been read at least once, the processor interface unit to receive a disposable information attribute indication from the processor when the processor delivers the disposable information to the processor interface unit.