公开(公告)号：WO03019391A3

公开(公告)日：2003-05-30

申请号：PCT/US0227043

申请日：2002-08-23

Applicant: INTEL CORP

Inventor： WEHAGE ERIC ,  AJANOVIC JASMIN ,  HARRIMAN DAVID J ,  LEE DAVID M ,  FANNING BLAISE ,  GREMEL BUCK ,  CRETA KEN ,  MOORE WAYNE A

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/12 ,  G06F13/14 ,  G06F13/24 ,  H04L1/18

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architectue, protocol and related methods are presented.

Abstract translation: 提出了一种增强的一般输入/输出通信架构，协议和相关方法。

公开(公告)号：WO0147174A2

公开(公告)日：2001-06-28

申请号：PCT/US0042169

申请日：2000-11-13

Applicant: INTEL CORP ,  OSBORNE RANDY B ,  AJANOVIC JASMIN

Inventor： OSBORNE RANDY B ,  AJANOVIC JASMIN

IPC: H04L1/00 ,  H04L7/00 ,  H04L7/04

CPC classification number: H04L1/0061 ,  H04L1/004 ,  H04L7/0083 ,  H04L7/048

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract translation: 或者（b）在发送代理向接收代理发送的数据的传送期间检测同步错误的方法：（a）当发送代理在一个或多个时钟信号中对数据进行编码时，（a）用数据奇偶校验功能编码的数据奇偶校验， ）标题奇偶校验，当发送代理编码一个或多个时钟信号中的标题信息时，用标题奇偶校验功能编码。 当接收方：（a）被配置为接收数据奇偶校验并且实际接收到标题奇偶校验时，或者（b）被配置为接收标题奇偶校验并实际接收数据奇偶校验，则检测到同步错误状况。

公开(公告)号：WO2009045884A3

公开(公告)日：2009-06-25

申请号：PCT/US2008077819

申请日：2008-09-26

Applicant: INTEL CORP ,  WAGH MAHESH ,  AJANOVIC JASMIN

Inventor： WAGH MAHESH ,  AJANOVIC JASMIN

IPC: G06F12/08

CPC classification number: G06F12/08 ,  G06F12/023 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/152

Abstract: Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described. In one embodiment, a hint provided by an endpoint device may be utilized to update information stored in an I/O cache. Such information may be utilized for implementation of a more efficient replacement policy in an embodiment. Other embodiments are also disclosed.

Abstract translation: 描述了与在虚拟化环境中改善地址翻译缓存和/或输入/输出（I / O）缓存性能有关的方法和装置。 在一个实施例中，可以利用由端点设备提供的提示来更新存储在I / O高速缓存中的信息。 在一个实施例中，可以利用这样的信息来实现更有效的替换策略。 其他实施例也被公开。

公开(公告)号：WO0131460A9

公开(公告)日：2002-07-04

申请号：PCT/US0029275

申请日：2000-10-23

Applicant: INTEL CORP ,  AJANOVIC JASMIN ,  HARRIMAN DAVID J

Inventor： AJANOVIC JASMIN ,  HARRIMAN DAVID J

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4208 ,  G06F13/4022

Abstract: An interface to transfer data between a memory control hub and an input/output control hub of a chipset within a computer system. One embodiment of the interface includes a bi-directional data signal path and a pair of source synchronous strobe signals. The data signal path transmits data in packets via split transactions. In addition, the packets include a request packet and a completion packet, if necessary. Furthermore, in one embodiment, the request packets include a transaction descriptor.

Abstract translation: 用于在计算机系统内的存储器控​​制集线器和芯片组的输入/输出控制集线器之间传送数据的接口。 接口的一个实施例包括双向数据信号路径和一对源同步选通信号。 数据信号路径通过分组事务发送数据包。 此外，如果需要，分组包括请求分组和完成分组。 此外，在一个实施例中，请求分组包括事务描述符。

公开(公告)号：EP0870240A4

公开(公告)日：2001-10-24

申请号：EP96924504

申请日：1996-07-15

Applicant: INTEL CORP

Inventor： AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

IPC: G06F13/362 ,  G06F13/00 ,  G06F13/36

CPC classification number: G06F13/362

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

公开(公告)号：EP1127319A4

公开(公告)日：2004-04-14

申请号：EP99961565

申请日：1999-11-02

Applicant: INTEL CORP

Inventor： HARRIMAN DAVID J ,  AJANOVIC JASMIN

IPC: G06F3/00 ,  G06F13/14 ,  H04L12/56 ,  H04L29/06 ,  H04L29/10

CPC classification number: G06F13/4022 ,  G06F13/423

Abstract: One embodiment of an apparatus for communicating transaction types between hubs (130, 160) in a computer system (100) includes a data path input/output unit (135, 165) to output a packet header (500). The packet header includes a request/completion field (31) to indicate whether the packet header (500) is a request packet header or a completion packet header. The packet header (500) also includes a read/write field (30) to indicate whether the packet header (500) is for a read packet or for a write packet. The read/write field (30) further indicates whether a length of data is to follow the packet header. The packet header further includes a data length field (8-13) to indicate the length of data.

公开(公告)号：WO2010129096A3

公开(公告)日：2011-01-13

申请号：PCT/US2010027604

申请日：2010-03-17

Applicant: INTEL CORP ,  WAGH MAHESH ,  SINGHAL ABHISHEK ,  AJANOVIC JASMIN

Inventor： WAGH MAHESH ,  SINGHAL ABHISHEK ,  AJANOVIC JASMIN

IPC: G06F13/42

CPC classification number: H04L69/22 ,  G06F13/385 ,  Y02B60/1228 ,  Y02B60/1235 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed

Abstract translation: 在一个实施例中，本发明包括在第一半导体芯片上的结构，用于根据片上协议与芯片上的至少一个代理通信，以及耦合到该结构的分组层，以从该结构接收命令和数据信息 多个链路，并将该信息分组成一个数据包，以便通过一个封包内分组化链路从芯片传输到另一个管芯。 描述和要求保护其他实施例

公开(公告)号：WO2010117518A3

公开(公告)日：2011-01-13

申请号：PCT/US2010026078

申请日：2010-03-03

Applicant: INTEL CORP ,  FANG ZHEN ,  WAGH MAHESH ,  AJANOVIC JASMIN ,  ESPIG MICHAEL E ,  IYER RAVISHANKAR

Inventor： FANG ZHEN ,  WAGH MAHESH ,  AJANOVIC JASMIN ,  ESPIG MICHAEL E ,  IYER RAVISHANKAR

IPC: G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F15/16

CPC classification number: G06F12/1036 ,  G06F12/0292 ,  G06F12/0888 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/109 ,  G06F2212/206

Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.

Abstract translation: 描述了用于控制片上系统结构（OSF）块的方法和装置。 在一个实施例中，响应于用户级请求可以存储对应于物理地址的影子地址，并且逻辑电路（例如，存在于OSF中）可以从影子地址确定物理地址。 还公开了其它实施例。

公开(公告)号：WO03030436A3

公开(公告)日：2003-06-19

申请号：PCT/US0230964

申请日：2002-09-26

Applicant: INTEL CORP

Inventor： HARRIMAN DAVID ,  AJANOVIC JASMIN ,  GREMEL BUCK

IPC: G06F11/00 ,  G06F15/163 ,  H04L1/00 ,  H04L1/18 ,  H04L1/22 ,  H04L12/56 ,  H04L29/08

CPC classification number: H04L1/1809 ,  H04L1/0061 ,  H04L1/0072 ,  H04L47/31 ,  H04L2001/0094

Abstract: If a switching or bridging equipment in a point-to-point architecture receives a datagram which is deemed to be definitive, it modifies the packet to indicate that an error exists, before forwarding it to its destination. The header and payload of the datagram are handled differently, and the datagram may not be modified if error is detected in the header only. If the receiver detects a tailer in a datagram, it treats it as containing corrupt content.

Abstract translation: 如果点对点架构中的交换或桥接设备接收到被认为是确定的数据报，则在将数据报转发到其目的地之前，修改数据包以指示存在错误。 数据报的报头和有效载荷被不同地处理，并且如果在报头中仅检测到错误，则数据报可能不被修改。 如果接收机检测到数据报中的分片，则将其视为包含损坏的内容。

公开(公告)号：WO9711418A3

公开(公告)日：1997-05-09

申请号：PCT/US9611716

申请日：1996-07-15

Applicant: INTEL CORP ,  AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

Inventor： AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

IPC: G06F13/362 ,  G06F

CPC classification number: G06F13/362

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.