公开(公告)号：GB2510763A

公开(公告)日：2014-08-13

申请号：GB201408844

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： FANNING BLAISE ,  QAWAMI SHEKOUFEH ,  TETRICK RAYMOND SCOTT ,  HADY FRANK T

IPC: G06F12/02 ,  G06F12/08

Abstract: Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.

公开(公告)号：AT428970T

公开(公告)日：2009-05-15

申请号：AT04257322

申请日：2004-11-25

Applicant: INTEL CORP

Inventor： SETHI PRASHANT ,  CRETA KENNETH C ,  TETRICK RAYMOND SCOTT

IPC: G06F9/445 ,  G06F15/16 ,  G06F13/40

Abstract: The ability to configure an integrated device with a decoder in a processor or network component according to PCI or PCI Express interconnects.

公开(公告)号：GB2473348B

公开(公告)日：2012-10-17

申请号：GB201015977

申请日：2009-06-24

Applicant: INTEL CORP

Inventor： TETRICK RAYMOND SCOTT ,  JUENEMANN DALE J ,  BRENNAN ROBERT

IPC: G06F12/08

Abstract: In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.

公开(公告)号：GB2473149B

公开(公告)日：2012-10-17

申请号：GB201015976

申请日：2009-06-09

Applicant: INTEL CORP

Inventor： JUENEMANN DALE J ,  HOWES JORDAN ,  MATTHEWS JEANNA ,  WELLS STEVEN ,  HINTON GLENN ,  PINTO OSCAR P ,  TETRICK RAYMOND SCOTT

IPC: G06F12/08 ,  G06F13/16

Abstract: In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.

公开(公告)号：GB2468455B

公开(公告)日：2012-08-01

申请号：GB201010828

申请日：2008-12-01

Applicant: INTEL CORP

Inventor： TETRICK RAYMOND SCOTT ,  HINTON GLENN ,  JUENEMANN DALE

IPC: G11B20/12 ,  G06F3/06 ,  G11B20/10 ,  G11B21/02

Abstract: In some embodiments a beginning portion of a disk drive file fragment is stored in a memory, and the beginning portion of the disk drive file fragment is accessed from the memory. Other embodiments are described and claimed.

公开(公告)号：HK1075111A1

公开(公告)日：2005-12-02

申请号：HK05109134

申请日：2005-10-17

Applicant: INTEL CORP

Inventor： SETHI PRASHANT ,  CRETA KENNETH C ,  TETRICK RAYMOND SCOTT

IPC: G06F15/16 ,  G06F20090101 ,  G06F9/445 ,  G06F13/40

Abstract: The ability to configure an integrated device with a decoder in a processor or network component according to PCI or PCI Express interconnects.

公开(公告)号：GB2473348A

公开(公告)日：2011-03-09

申请号：GB201015977

申请日：2009-06-24

Applicant: INTEL CORP

Inventor： TETRICK RAYMOND SCOTT ,  JUENEMANN DALE J ,  BRENNAN ROBERT

IPC: G06F12/08

Abstract: In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.

公开(公告)号：GB2473149A

公开(公告)日：2011-03-02

申请号：GB201015976

申请日：2009-06-09

Applicant: INTEL CORP

Inventor： JUENEMANN DALE J ,  HOWES JORDAN ,  MATTHEWS JEANNA ,  WELLS STEVEN ,  HINTON GLENN ,  PINTO OSCAR P ,  TETRICK RAYMOND SCOTT

IPC: G06F12/08 ,  G06F13/16

Abstract: In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.

公开(公告)号：DE602004020579D1

公开(公告)日：2009-05-28

申请号：DE602004020579

申请日：2004-11-25

Applicant: INTEL CORP

Inventor： SETHI PRASHANT ,  CRETA KENNETH C ,  TETRICK RAYMOND SCOTT

IPC: G06F9/445 ,  G06F15/16 ,  G06F13/40

Abstract: The ability to configure an integrated device with a decoder in a processor or network component according to PCI or PCI Express interconnects.

公开(公告)号：DE3500248A1

公开(公告)日：1986-07-10

申请号：DE3500248

申请日：1985-01-05

Applicant: INTEL CORP

Inventor： FARRELL ROBERT LELAND ,  SARABI ALIREZA ,  TETRICK RAYMOND SCOTT

IPC: G06F13/376 ,  G06F13/42 ,  G06F13/40 ,  H04L25/02

Abstract: The bus structure comprises both a parallel bus (35) and a series bus (37), which connect to one another data processing units (25, 26) and peripheral devices (30), jointly referred to as "stations", in order to permit the interchange of data and messages at high speed using a minimum of "handshake" events before the actual data transmission. The serial and parallel bus protocols are controlled by message control devices (44, 50), which are coupled to each participating station. A local bus (56) is coupled to processing stations (25, 26) within the system in such a way that access can be made to local memories (54) and secondary processing resources (57) without adversely affecting the data traffic via the parallel bus (35). A direct access by other bus stations to resources (54) coupled to the local bus (56) of one station is likewise controlled by the message control device (44).