公开(公告)号：US10998270B2

公开(公告)日：2021-05-04

申请号：US16337794

申请日：2016-10-28

Applicant: INTEL CORPORATION

Inventor： Seung Hoon Sung ,  Glenn A. Glass ,  Van H. Le ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L27/092 ,  H01L21/768 ,  H01L21/8238

Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.

公开(公告)号：US20200219804A1

公开(公告)日：2020-07-09

申请号：US16243790

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ashish Agrawal ,  Kevin L. Lin ,  Abhishek Sharma ,  Carl Naylor ,  Urusa Alaan

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/12 ,  H01L29/417 ,  H01L29/24 ,  H01L29/423 ,  H01L23/535 ,  H01L29/786 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L21/4763

Abstract: Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.

公开(公告)号：US20200091287A1

公开(公告)日：2020-03-19

申请号：US16131520

申请日：2018-09-14

Applicant: INTEL CORPORATION

Inventor： Glenn Glass ,  Anand Murthy ,  Cory Bomberger ,  Tahir Ghani ,  Jack Kavalieros ,  Siddharth Chouksey ,  Seung Hoon Sung ,  Biswajeet Guha ,  Ashish Agrawal

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8238

Abstract: A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.

公开(公告)号：US10593785B2

公开(公告)日：2020-03-17

申请号：US15771998

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Sanaz K. Gardner ,  Willy Rachmady ,  Van H. Le ,  Matthew V. Metz ,  Seiyon Kim ,  Ashish Agrawal ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L27/092 ,  H01L29/267 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20

Abstract: A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.

公开(公告)号：US20190341453A1

公开(公告)日：2019-11-07

申请号：US16465758

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Glenn A. Glass ,  Harold W. Kennel ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L21/02

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.

公开(公告)号：US10249742B2

公开(公告)日：2019-04-02

申请号：US15576468

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Van H. Le ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Ashish Agrawal ,  Matthew V. Metz ,  Willy Rachmady ,  Marc C. French ,  Jack T. Kavalieros ,  Rafael Rios ,  Seiyon Kim ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  James M. Powers ,  Sherry R. Taft

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10

Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

公开(公告)号：US20250031362A1

公开(公告)日：2025-01-23

申请号：US18907358

申请日：2024-10-04

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert Dewey ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Jack Kavalieros

IPC: H10B12/00 ,  H01L21/683 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

公开(公告)号：US20240136277A1

公开(公告)日：2024-04-25

申请号：US18395192

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/768 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/76251 ,  H01L21/76804 ,  H01L27/1203

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US11887988B2

公开(公告)日：2024-01-30

申请号：US16529643

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Jack Kavalieros ,  Anand Murthy ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Cheng-Ying Huang ,  Cory Bomberger

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L27/1207 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/66742

Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.

公开(公告)号：US20230139255A1

公开(公告)日：2023-05-04

申请号：US17517076

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Gilbert Dewey ,  Siddharth Chouksey ,  Jack T. Kavalieros ,  Cheng-Ying Huang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/165 ,  H01L27/092

Abstract: A gate-all-around transistor device includes a body including a semiconductor material, and a gate structure at least in part wrapped around the body. The gate structure includes a gate electrode and a gate dielectric between the body and the gate electrode. The body is between a source region and a drain region. A first spacer is between the source region and the gate electrode, and a second spacer is between the drain region and the gate electrode. In an example, the first and second spacers include germanium and oxygen. The body can be, for instance, a nanoribbon, nanosheet, or nanowire.