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公开(公告)号：US20220157010A1
公开(公告)日：2022-05-19
申请号：US17533531
申请日：2021-11-23
Applicant: INTEL CORPORATION
Inventor： Carsten BENTHIN , Sven WOOP
Abstract: An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.
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公开(公告)号：US20210287431A1
公开(公告)日：2021-09-16
申请号：US16819118
申请日：2020-03-15
Applicant: Intel Corporation
Inventor： Sven WOOP , Karthik VAIDYANATHAN , Carsten BENTHIN
Abstract: Apparatus and method for lossy displaced mesh compression. For example, one embodiment of an apparatus comprises: displacement mapping circuitry/logic to generate an original displacement-mapped mesh by performing a displacement mapping of a plurality of vertices of a base subdivision mesh; and mesh compression circuitry/logic to compress the original displacement-mapped mesh, the mesh compression circuitry/logic comprising a quantizer to quantize the displacement mapping of the plurality of vertices in view of a base mesh to generate a displacement array.
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公开(公告)号：US20210287429A1
公开(公告)日：2021-09-16
申请号：US16819120
申请日：2020-03-15
Applicant: Intel Corporation
Inventor： Karthik VAIDYANATHAN , Carsten BENTHIN , Sven WOOP
Abstract: Apparatus and method for box-box testing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged BVH nodes; traversal circuitry to traverse query boxes through the BVH, the traversal circuitry to read a BVH node from a top of a BVH node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum X, Y, and Z coordinates of the BVH node and the query box and to generate an overlap indication if overlap is detected for each of the X, Y, and Z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and/or logic to sort the BVH node within a set of one or more additional BVH nodes based on the distance value.
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公开(公告)号：US20210241431A1
公开(公告)日：2021-08-05
申请号：US17171925
申请日：2021-02-09
Applicant: Intel Corporation
Inventor： Carson BROWNLEE , Ingo WALD , Attila AFRA , Johannes GUENTHER , Jefferson AMSTUTZ , Carsten BENTHIN
Abstract: Apparatus and method for denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment of a system or apparatus comprises: A system comprising: a plurality of nodes to perform ray tracing operations; a dispatcher node to dispatch graphics work to the plurality of nodes, each node to perform ray tracing to render a region of an image frame; at least a first node of the plurality comprising: a ray-tracing renderer to perform ray tracing to render a first region of the image frame; and a denoiser to perform denoising of the first region using a combination of data associated with the first region and data associated with a region outside of the first region, at least some of the data associated with the region outside of the first region to be retrieved from at least one other node.
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公开(公告)号：US20210005009A1
公开(公告)日：2021-01-07
申请号：US16929671
申请日：2020-07-15
Applicant: INTEL CORPORATION
Inventor： Karthik VAIDYANATHAN , Sven WOOP , Carsten BENTHIN
Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; traversal/intersection circuitry to traverse one or more of the rays through the hierarchically arranged nodes of the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes; and traversal tracking circuitry to maintain a path encoding array to store path data related to the current traversal path, the path data comprising an index of a currently traversed child node; wherein the traversal/intersection circuitry is to prevent one or more subsequent rays from re-intersecting primitives from which they originated and/or avoid re-traversing the current traversal path based on the path data in the path encoding array.
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Patent Agency Ranking
公开(公告)号：US20240087208A1
公开(公告)日：2024-03-14
申请号：US18372783
申请日：2023-09-26
Applicant: INTEL CORPORATION
Inventor： Sven WOOP , Attila AFRA , Carsten BENTHIN , Ingo WALD , Johannes GUENTHER
CPC classification number: G06T15/005 , G06T1/20 , G06T15/06 , G06T17/00
Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
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公开(公告)号：US20230162428A1
公开(公告)日：2023-05-25
申请号：US17982766
申请日：2022-11-08
Applicant: INTEL CORPORATION
Inventor： Michael APODACA , Carsten BENTHIN , Kai XIAO , Carson BROWNLEE , Timothy ROWLEY , Joshua BARCZAK , Travis SCHLUESSLER
IPC: G06T15/06 , G06F16/901 , G06F7/14 , G06F9/38
CPC classification number: G06T15/06 , G06F16/9027 , G06F7/14 , G06F9/3877 , G06N3/02
Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.
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公开(公告)号：US20220366525A1
公开(公告)日：2022-11-17
申请号：US17707118
申请日：2022-03-29
Applicant: INTEL CORPORATION
Inventor： Carsten BENTHIN , Sven WOOP , Ingo WALD
Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.
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公开(公告)号：US20210407177A1
公开(公告)日：2021-12-30
申请号：US17368335
申请日：2021-07-06
Applicant: Intel Corporation
Inventor： Scott JANUS , Prasoonkumar SURTI , Karthik VAIDYANATHAN , Carsten BENTHIN , Philip LAWS
Abstract: Apparatus and method for ray tracing acceleration using a grid primitive. For example, one embodiment of an apparatus comprises: a grid primitive generator to generate a grid primitive comprising a plurality of adjacent interconnected primitives; a bitmask generator to generate a bitmask associated with the grid primitive, the bitmask comprising a plurality of bitmask values, each mask value associated with a primitive of the grid primitive; a ray tracing engine comprising traversal and intersection hardware logic to perform traversal and intersection operations in which rays are traversed through a hierarchical acceleration data structure and intersections between the rays and one or more of the adjacent interconnected primitives identified, wherein the ray tracing engine is to read the bitmask to determine a first set of primitives from the grid primitive on which to perform the traversal and intersection operations and a second set of primitives from the grid primitive on which the traversal and intersection operations will not be performed.
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公开(公告)号：US20210035349A1
公开(公告)日：2021-02-04
申请号：US16996208
申请日：2020-08-18
Applicant: INTEL CORPORATION
Inventor： Karthik VAIDYANATHAN , Michael APODACA , Thomas RAOUX , Carsten BENTHIN , Kai XIAO , Carson BROWNLEE , Joshua BARCZAK
Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.
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