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公开(公告)号：US10001964B2
公开(公告)日：2018-06-19
申请号：US14733169
申请日：2015-06-08
Applicant: Intel Corporation
Inventor： Sagar Pawar , Prakash Pillai
CPC classification number: G06F3/165 , H04L1/16 , H04R5/02 , H04R5/04 , H04R27/00 , H04R2420/05 , H04R2420/07 , H04W84/12 , H04W84/18
Abstract: Methods, devices and systems for handling Wi-Fi or Bluetooth signals in a wireless network are disclosed. Example embodiments include a method including the operations of receiving, by a speaker system comprising at least one processor and one or more output speakers, one or more encoded data streams over a wireless connection, decoding the one or more data streams and outputting the one or more decoded data streams through the one or more output speakers, and pausing outputting of the one or more decoded data streams upon determining a halting event.
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公开(公告)号：US12253966B2
公开(公告)日：2025-03-18
申请号：US17482786
申请日：2021-09-23
Applicant: Intel Corporation
Inventor： Prakash Pillai , Sagar Pawar , Raghavendra Nagaraj , Ovais Pir , Pannerkumar Rajagopal
Abstract: A Peripheral Component Interface Express (PCIe) card includes a circuit board, a device mounted on the circuit board, and a PCIe processor mounted on the circuit board. The PCIe processor is communicatively coupled to the device and a host processor of a host system. The PCIe processor is configured to detect a power signal on an auxiliary (AUX) power rail of the PCIe card. A periodic detection of a state of the device is performed based on detecting the power signal on the AUX power rail. A signal indicative of the state of the device is encoded for transmission to the host processor of the host system. PCIe link training is performed via a PCIe interface with the host system. The PCIe link training is initiated based on the signal indicative of the state of the device.
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公开(公告)号：US20220206591A1
公开(公告)日：2022-06-30
申请号：US17698712
申请日：2022-03-18
Applicant: Intel Corporation
Inventor： Sagar Pawar , Raghavendra Nagaraj , Prakash Pillai , Ovais Pir , Pannerkumar Rajagopal
Abstract: Methods and apparatus for adaptive keyboard scanning are disclosed. A disclosed example apparatus to adaptively control operation of a keyboard includes at least one memory, instructions, and processor circuitry. The processor circuitry is to determine whether to operate the keyboard in a first mode or in a second mode different from the first mode, the first mode corresponding to a first number of keys, the second mode corresponding to a second number of keys less than the first number of keys, and set the keyboard to operate in the first mode or the second mode based on the determination.
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公开(公告)号：US10653026B2
公开(公告)日：2020-05-12
申请号：US15864583
申请日：2018-01-08
Applicant: Intel Corporation
Inventor： Samarth Alva , Krishnakumar Varadarajan , Yogesh Channaiah , Prakash Pillai , Sagar Pawar , Aneesh Tuljapurkar , Raghavendra N
Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.
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15.发明申请公开(公告)号：US20180293291A1
公开(公告)日：2018-10-11
申请号：US15481733
申请日：2017-04-07
Applicant: INTEL CORPORATION
Inventor： Sagar C. Pawar , Prakash Pillai , Raghavendra N , Aneesh A. Tuljapurkar
CPC classification number: G06F17/30575 , G06F1/04 , H04J3/06 , H04L7/0008 , H04L7/0016 , H04L7/10
Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US09612792B2
公开(公告)日：2017-04-04
申请号：US14739954
申请日：2015-06-15
Applicant: Intel Corporation
Inventor： Sagar C. Pawar , Prakash Pillai
CPC classification number: G06F3/165
Abstract: Apparatuses, methods, and computer-readable media for dynamic configuration of audio production are described. Audio production nodes (“APNs”) may produce audio. The APNs and may be configured to be compliant with a Precision Time Protocol (“PTP”). The APNs may be configured to perform dynamic configuration of audio production. An APN may receive configuration-related information transmitted from one or more other APNs, such as in association with operation of the PTP. An APN, in response to receipt of this configuration-related data, may modify configuration settings used for its audio production such as modification of timing, tone, power, intensity, equalization settings, or other configuration settings. The APN may be configured to produce its own configuration-related data for use by other APNs to modify the other APNs' configuration settings. Other embodiments may be described and/or claimed.
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公开(公告)号：US12007823B2
公开(公告)日：2024-06-11
申请号：US17702504
申请日：2022-03-23
Applicant: Intel Corporation
Inventor： Pannerkumar Rajagopal , Raghavendra N , Ovais Pir , Prakash Pillai , Sagar C. Pawar
IPC: G06F1/32 , G06F1/3231
CPC classification number: G06F1/3231
Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.
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公开(公告)号：US20240004454A1
公开(公告)日：2024-01-04
申请号：US17809652
申请日：2022-06-29
Applicant: Intel Corporation
Inventor： Sagar C. Pawar , Pannerkumar Rajagopal , Raghavendra Nagaraj , Ovais F. Pir , Prakash Pillai
IPC: G06F1/3296 , G06F1/30
CPC classification number: G06F1/3296 , G06F1/30
Abstract: In an embodiment, a processor may include processing circuits to execute instructions. The processor may also include at least one circuit to: detect a management mode trigger event during operation of the processor in a first power state, the management mode trigger event to initiate a management mode in the processor; in response to a detection of the management mode trigger event, switch the processor from the first power state to a second power state; and after a switch of the processor from the first power state to the second power state, initiate the management mode in the processor. Other embodiments are described and claimed.
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公开(公告)号：US11720401B2
公开(公告)日：2023-08-08
申请号：US16832372
申请日：2020-03-27
Applicant: Intel Corporation
Inventor： Pannerkumar Rajagopal , Murali R Iyengar , Karunakara Kotary , Ovais Pir , Sagar C Pawar , Prakash Pillai , Raghavendra N , Aneesh A Tuljapurkar
IPC: G06F9/4401 , G06F9/50 , G06F9/54 , G06F12/1009 , G06T1/60
CPC classification number: G06F9/5016 , G06F9/4406 , G06F9/544 , G06F12/1009 , G06T1/60
Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.
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公开(公告)号：US20220391003A1
公开(公告)日：2022-12-08
申请号：US17702504
申请日：2022-03-23
Applicant: Intel Corporation
Inventor： Pannerkumar Rajagopal , Raghavendra N , Ovais Pir , Prakash Pillai , Sagar C. Pawar
IPC: G06F1/3231
Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.
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