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    Technologies for network device flow lookup management
    11.
    发明授权
    Technologies for network device flow lookup management 有权

    公开(公告)号：US10284470B2

    公开(公告)日：2019-05-07

    申请号：US14580801

    申请日：2014-12-23

    Applicant: Intel Corporation

    Inventor： Ren Wang ,  Namakkal N. Venkatesan ,  Aamer Jaleel ,  Tsung-Yuan C. Tai ,  Sameh Gobriel ,  Christian Maciocco

    IPC: H04L12/743 ,  H04L29/06 ,  H04L12/747

    Abstract: Technologies for managing network flow lookups of a network device include a network controller and a target device, each communicatively coupled to the network device. The network device includes a cache for a processor of the network device and a main memory. The network device additionally includes a multi-level hash table having a first-level hash table stored in the cache of the network device and a second-level hash table stored in the main memory of the network device. The network device is configured to determine whether to store a network flow hash corresponding to a network flow indicating the target device in the first-level or second-level hash table based on a priority of the network flow provided to the network device by the network controller.

    Processors and methods for managing cache tiering with gather-scatter vector semantics
    12.
    发明授权
    Processors and methods for managing cache tiering with gather-scatter vector semantics 有权

    公开(公告)号：US10268580B2

    公开(公告)日：2019-04-23

    申请号：US15282483

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Kshitij A. Doshi ,  Namakkal N. Venkatesan ,  Ren Wang ,  Andrew J. Herdrich

    IPC: G06F9/30 ,  G06F12/128 ,  G06F12/0811

    Abstract: Processors and methods implementing a machine instruction to perform cache line demotion on multiple cache lines to enable efficient sharing of cache lines between processor cores. One general aspect includes a processor comprising: a plurality of hardware processor cores, where each of the hardware processor cores to include a first cache. The processor also includes a second cache, communicatively coupled to and shared by the plurality of hardware processor cores. The processor to support a first machine instruction, the first machine instruction to include a vector register operand identifying a vector register which contains a plurality of data elements each used to identify a cache line. An execution of the first machine instruction by one of the plurality of hardware processor cores to cause a plurality of identified cache lines to be demoted, such that the demoted cache lines are moved from the first cache to the second cache.

    DENIAL OF SERVICE MITIGATION WITH TWO-TIER HASH
    13.
    发明申请
    DENIAL OF SERVICE MITIGATION WITH TWO-TIER HASH 审中-公开

    公开(公告)号：US20190104150A1

    公开(公告)日：2019-04-04

    申请号：US15720821

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Sameh Gobriel ,  Christian Maciocco ,  Byron Marohn ,  Ren Wang ,  Tsung-Yuan C. Tai

    IPC: H04L29/06 ,  G06F17/30

    Abstract: A computing apparatus for providing a node within a distributed network function, including: a hardware platform; a network interface to communicatively couple to at least one other peer node of the distributed network function; a distributor function including logic to operate on the hardware platform, including a hashing module configured to receive an incoming network packet via the network interface and perform on the incoming network packet a first-level hash of a two-level hash, the first level hash being a lightweight hash with respect to a second-level hash, the first level hash to deterministically direct a packet to one of the nodes of the distributed network function as a directed packet; and a denial of service (DoS) mitigation engine to receive notification of a DoS attack, identify a DoS packet via the first-level hash, and prevent the DoS packet from reaching the second-level hash.

    TECHNOLOGIES FOR A LEAST RECENTLY USED CACHE REPLACEMENT POLICY USING VECTOR INSTRUCTIONS
    15.
    发明申请
    TECHNOLOGIES FOR A LEAST RECENTLY USED CACHE REPLACEMENT POLICY USING VECTOR INSTRUCTIONS 审中-公开

    公开(公告)号：US20190042471A1

    公开(公告)日：2019-02-07

    申请号：US16059147

    申请日：2018-08-09

    Applicant: Intel Corporation

    Inventor： Ren Wang ,  Yipeng Wang ,  Tsung-Yuan Tai ,  Cristian Florin Dumitrescu ,  Xiangyang Guo

    IPC: G06F12/123 ,  G06F12/128 ,  G06F12/126 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/0864 ,  G06F9/30

    Abstract: Technologies for least recently used (LRU) cache replacement include a computing device with a processor with vector instruction support. The computing device retrieves a bucket of an associative cache from memory that includes multiple entries arranged from front to back. The bucket may be a 256-bit array including eight 32-bit entries. For lookups, a matching entry is located at a position in the bucket. The computing device executes a vector permutation processor instruction that moves the matching entry to the front of the bucket while preserving the order of other entries of the bucket. For insertion, an inserted entry is written at the back of the bucket. The computing device executes a vector permutation processor instruction that moves the inserted entry to the front of the bucket while preserving the order of other entries. The permuted bucket is stored to the memory. Other embodiments are described and claimed.

    TECHNOLOGIES FOR DISTRIBUTED ROUTING TABLE LOOKUP
    18.
    发明申请
    TECHNOLOGIES FOR DISTRIBUTED ROUTING TABLE LOOKUP 审中-公开

    公开(公告)号：US20180019943A1

    公开(公告)日：2018-01-18

    申请号：US15717287

    申请日：2017-09-27

    Applicant: Intel Corporation

    Inventor： Sameh Gobriel ,  Ren Wang ,  Christian Maciocco ,  Tsung-Yuan Tai

    IPC: H04L12/721 ,  H04L12/755 ,  H04L12/743 ,  H04L12/751 ,  H04L12/725

    CPC classification number: H04L45/44 ,  H04L45/02 ,  H04L45/021 ,  H04L45/306 ,  H04L45/7453

    Abstract: Technologies for distributed table lookup via a distributed router includes an ingress computing node, an intermediate computing node, and an egress computing node. Each computing node of the distributed router includes a forwarding table to store a different set of network routing entries obtained from a routing table of the distributed router. The ingress computing node generates a hash key based on the destination address included in a received network packet. The hash key identifies the intermediate computing node of the distributed router that stores the forwarding table that includes a network routing entry corresponding to the destination address. The ingress computing node forwards the received network packet to the intermediate computing node for routing. The intermediate computing node receives the forwarded network packet, determines a destination address of the network packet, and determines the egress computing node for transmission of the network packet from the distributed router.

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