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    SAVE-RESTORE CIRCUITRY WITH METAL-FERROELECTRIC-METAL DEVICES
    13.
    发明申请
    SAVE-RESTORE CIRCUITRY WITH METAL-FERROELECTRIC-METAL DEVICES 审中-公开

    公开(公告)号：US20190043549A1

    公开(公告)日：2019-02-07

    申请号：US16144896

    申请日：2018-09-27

    Applicant: Intel Corporation

    Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Huichu Liu ,  Dileep J. Kurian ,  Uygar E. Avci ,  Tanay Karnik ,  Ian A. Young

    IPC: G11C11/22 ,  G11C11/413 ,  G06F1/32

    Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

    EFFICIENT SOFTMAX COMPUTATION WITH NO LOSS IN ACCURACY
    14.
    发明公开
    EFFICIENT SOFTMAX COMPUTATION WITH NO LOSS IN ACCURACY 审中-公开

    公开(公告)号：US20240320490A1

    公开(公告)日：2024-09-26

    申请号：US18734487

    申请日：2024-06-05

    Applicant: Intel Corporation

    Inventor： Jainaveen Sundaram Priya ,  Prerna Budhkar ,  Vui Seng Chua ,  Srivatsa Rangachar Srinivasa ,  Tanay Karnik

    IPC: G06N3/08 ,  G06N3/048

    CPC classification number: G06N3/08 ,  G06N3/048

    Abstract: A modified 2-pass version of the SoftMax operation can be implemented to address reduce computational cost without loss of accuracy, in particular for deep learning neural networks such as transformer-based neural networks and large language models (LLMs). The first pass is modified to include two scalar operations at the end. At the end of the first pass, a first scalar operation is performed to calculate a logarithm of the denominator, and a second scalar operation is performed to calculate an operand value based on a sum of the logarithm of the denominator and the maximum value. The second pass is modified to perform addition and exponentiation. In the second pass, an element of an input tensor is subtracted by the operand value to obtain an exponent, and a base is raised to the exponent. The second pass avoids divisions.

    SHELL STRUCTURE FOR INSULATION OF A THROUGH-SUBSTRATE INTERCONNECT
    18.
    发明申请
    SHELL STRUCTURE FOR INSULATION OF A THROUGH-SUBSTRATE INTERCONNECT 审中-公开

    公开(公告)号：US20170287781A1

    公开(公告)日：2017-10-05

    申请号：US15085925

    申请日：2016-03-30

    Applicant: Intel Corporation

    Inventor： Tanay Karnik ,  William Wahby

    IPC: H01L21/768 ,  H01L23/528

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/528

    Abstract: Techniques and mechanisms for providing electrical insulation of a through-substrate interconnect (TI). In an embodiment, the TI extends between a first side of the substrate and a second side of the substrate opposite the first side. The substrate has formed therein a conductive shell structure that extends at least partially around a periphery of the TI. A first dielectric liner structure is disposed between the conductive shell structure and a bulk material of the substrate. A second dielectric liner structure is disposed between the conductive shell structure and the TI. In another embodiment, a voltage of the conductive shell structure is allowed to float while the TI exchanges a signal or a supply voltage.

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