公开(公告)号：US20180351861A1

公开(公告)日：2018-12-06

申请号：US15969017

申请日：2018-05-02

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Parthasarathy Sarangam ,  Eric Mann ,  Daniel Cohn

IPC: H04L12/741 ,  H04L12/721 ,  H04L12/863 ,  H04L12/801 ,  H04L12/873

CPC classification number: H04L45/74 ,  H04L45/38 ,  H04L47/115 ,  H04L47/52 ,  H04L47/54

Abstract: Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.

公开(公告)号：US20180004703A1

公开(公告)日：2018-01-04

申请号：US15200260

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Anil Vasudevan ,  David Harriman

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/4072

Abstract: A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.

公开(公告)号：US09621633B2

公开(公告)日：2017-04-11

申请号：US13836959

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Yadong Li ,  Anil Vasudevan ,  Linden Cornett

IPC: G06F15/16 ,  H04L29/08 ,  G06F13/38

CPC classification number: H04L67/10 ,  G06F13/385

Abstract: Generally, this disclosure relates to low latency networking. A system may include processor circuitry comprising at least one processor; memory circuitry configured to store an application, a receive queue and a networking stack comprising a network device driver; a network controller comprising a flow director, the network controller configured to couple the host device to at least one link partner and the flow director configured to store one or more selected received packets in the receive queue, the selecting based, at least in part, on a packet flow identifier; and a network device driver configured to identify the receive queue in response to a polling request comprising the packet flow identifier; poll the receive queue; and process each received packet stored in the receive queue.

公开(公告)号：US09026682B2

公开(公告)日：2015-05-05

申请号：US13713635

申请日：2012-12-13

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20190391940A1

公开(公告)日：2019-12-26

申请号：US16457110

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Sridhar Samudrala ,  Parthasarathy Sarangam ,  Kiran Patil

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/4401 ,  G06F3/06

Abstract: Technologies for interrupt disassociated queuing for multi-queue input/output devices includes determining whether a network packet has arrived in an interrupt-disassociated queue and delivering the network packet to an application managed by the compute node. The application is associated with an application thread and the interrupt-disassociated queue may be in a polling mode. Subsequently, in response to a transition event, the interrupt-disassociated queue may be transitioned to an interrupt mode.

公开(公告)号：US10353631B2

公开(公告)日：2019-07-16

申请号：US13948715

申请日：2013-07-23

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Dave B. Minturn ,  Kiran Patil

IPC: G06F15/167 ,  G06F3/06

Abstract: Examples are disclosed for moving data between a network input/output (I/O) device and a storage subsystem and/or storage device. In some examples, a network I/O device coupled to a host device may receive a data frame including a request to access a storage subsystem or storage device. The storage subsystem and/or storage device may be located with the network I/O device or separately coupled to the host device through a storage controller. One or more buffers maintained in a cache for processor circuitry may be used to exchange control information or stage data associated with the data frame to avoid or eliminate use of system memory to move data to or from the storage subsystem and/or storage device. Other examples are described and claimed.

公开(公告)号：US10346326B2

公开(公告)日：2019-07-09

申请号：US15008083

申请日：2016-01-27

Applicant: Intel Corporation

Inventor： Yadong Li ,  Linden Cornett ,  Manasi Deval ,  Anil Vasudevan ,  Parthasarathy Sarangam

IPC: G06F3/00 ,  G06F13/24 ,  H04L29/06

Abstract: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.

公开(公告)号：US20170187640A1

公开(公告)日：2017-06-29

申请号：US14998138

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Kiran A. Patil ,  Arun Chekhov Ilango

IPC: H04L12/863 ,  H04L12/26

Abstract: In an example, there is disclosed a computing apparatus, having: a network interface configured to provide a plurality of queues; an application; and one or more logic elements comprising a queuing engine to: inspect an incoming packet; and assign the incoming packet to a dedicated queue for the application based on a classifier. There is also disclosed a method of providing a queuing engine, and one or more tangible, non-transitory computer-readable storage mediums having stored thereon executable instructions for providing a queuing engine.

公开(公告)号：US09608842B2

公开(公告)日：2017-03-28

申请号：US14106253

申请日：2013-12-13

Applicant: Intel Corporation

Inventor： Ygdal Naouri ,  Ronen Chayat ,  Ben-Zion Friedman ,  Parthasarathy Sarangam ,  Anil Vasudevan ,  Alain Gravel

IPC: G06F3/00 ,  H04L12/64

CPC classification number: H04L12/6418

Abstract: An embodiment may include circuitry that may provide, at least in part, at least one indication that at least one portion of data is available for processing by at least one data processor. The at least one indication may be provided, at least in part, prior to the entirety of the at least one portion of the data being available for the processing by the at least one data processor. The at least one data processor may begin the processing in response, at least in part, to the at least one indication. Many alternatives, variations, and modifications are possible.

公开(公告)号：US09602443B2

公开(公告)日：2017-03-21

申请号：US14557020

申请日：2014-12-01

Applicant: Intel Corporation

Inventor： Linden Cornett ,  David B. Minturn ,  Sujoy Sen ,  Hemal V. Shah ,  Anshuman Thakur ,  Gary Tsao ,  Anil Vasudevan

IPC: H04L12/54 ,  H04L12/861 ,  H04L12/863 ,  H04L29/06

CPC classification number: H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

Abstract: In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.