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公开(公告)号:US11664596B2
公开(公告)日:2023-05-30
申请号:US17373926
申请日:2021-07-13
Applicant: Intel Corporation
Inventor: Sidharth Dalmia , Trang Thai , William James Lambert , Zhichao Zhang , Jiwei Sun
CPC classification number: H01Q9/0407 , H01Q1/085 , H01Q1/2283 , H01Q11/14
Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an antenna patch support including a flexible portion; an integrated circuit (IC) package coupled to the antenna patch support; and an antenna patch coupled to the antenna patch support.
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公开(公告)号:US20230088928A1
公开(公告)日:2023-03-23
申请号:US17483444
申请日:2021-09-23
Applicant: Intel Corporation
Inventor: Jung Kyu Han , Jiwei Sun , Zhiguo Qian , Srinivas Pietambaram
IPC: H01L23/498 , H01L23/15 , H01L49/02 , H01L21/48
Abstract: Embedded glass cores in package substrates and related methods are disclosed herein including an integrated circuit including a substrate having a first side and a second side opposite the first side, a plurality of vias disposed within the substrate to electrically couple corresponding contacts on the first and second sides of the substrate, a glass core surrounding a first via of the plurality of vias, and an organic core surrounding a second via of the plurality of vias, the second via different than the first via.
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公开(公告)号:US11482471B2
公开(公告)日:2022-10-25
申请号:US16287728
申请日:2019-02-27
Applicant: Intel Corporation
Inventor: Cheng Xu , Junnan Zhao , Zhimin Wan , Ying Wang , Yikang Deng , Chong Zhang , Jiwei Sun , Zhenguo Jiang , Kyu-Oh Lee
IPC: H01L23/46 , H01L23/467 , H05K1/18 , H05K1/02 , H05K3/32 , H01L23/473 , H01L23/66 , H01L23/31
Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.
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公开(公告)号:US11095045B2
公开(公告)日:2021-08-17
申请号:US16493520
申请日:2017-03-30
Applicant: Intel Corporation
Inventor: Zhichao Zhang , Jiwei Sun , Kemal Aygun
Abstract: Length matching and phase matching between circuit paths of differing lengths is disclosed. Two signals are specified to arrive at respective path destinations at a predetermined time and with a predetermined phase. An IC provides a first electronic signal over a first conductive path to a first destination and a second electronic signal over a second conductive path to a second destination. A first slow wave structure comprises the first conductive path and a second slow wave structure comprises the second conductive path. The effective relative permittivity of the first slow wave structure is tuned such that the first electronic signal arrives at its destination at a first time and at a first phase, and the effective relative permittivity of the second slow wave structure is tuned such that the second electronic signal arrives at its destination at a second time and at a second phase.
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公开(公告)号:US20200014122A1
公开(公告)日:2020-01-09
申请号:US16493520
申请日:2017-03-30
Applicant: Intel Corporation
Inventor: Zhichao Zhang , Jiwei Sun , Kemal Aygun
Abstract: Length matching and phase matching between circuit paths of differing lengths is disclosed. Two signals are specified to arrive at respective path destinations at a predetermined time and with a predetermined phase. An IC provides a first electronic signal over a first conductive path to a first destination and a second electronic signal over a second conductive path to a second destination. A first slow wave structure comprises the first conductive path and a second slow wave structure comprises the second conductive path. The effective relative permittivity of the first slow wave structure is tuned such that the first electronic signal arrives at its destination at a first time and at a first phase, and the effective relative permittivity of the second slow wave structure is tuned such that the second electronic signal arrives at its destination at a second time and at a second phase.
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公开(公告)号:US20190372229A1
公开(公告)日:2019-12-05
申请号:US16000795
申请日:2018-06-05
Applicant: Intel Corporation
Inventor: Sidharth Dalmia , Trang Thai , William James Lambert , Zhichao Zhang , Jiwei Sun
Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an antenna patch support including a flexible portion; an integrated circuit (IC) package coupled to the antenna patch support; and an antenna patch coupled to the antenna patch support.
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17.
公开(公告)号:US12288744B2
公开(公告)日:2025-04-29
申请号:US17742816
申请日:2022-05-12
Applicant: Intel Corporation
Inventor: Ji Yong Park , Kyu Oh Lee , Yikang Deng , Zhichao Zhang , Liwei Cheng , Andrew James Brown , Cheng Xu , Jiwei Sun
IPC: H01L23/498 , H01L21/48 , H01L23/00
Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.
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公开(公告)号:US12009320B2
公开(公告)日:2024-06-11
申请号:US16596383
申请日:2019-10-08
Applicant: Intel Corporation
Inventor: Zhiguo Qian , Cemil Geyik , Jiwei Sun , Gang Duan , Kemal Aygün
IPC: H01L23/49 , H01L23/498 , H01L23/64
CPC classification number: H01L23/645 , H01L23/49822 , H01L23/49838 , H01L23/49866
Abstract: Embodiments include package substrates and a semiconductor package with such package substrates. A package substrate includes a first conductive layer in a first magnetic layer, and a second magnetic layer over the first magnetic layer, where the first and second magnetic layers include magnetic materials. The package substrate also includes a second conductive layer in the second magnetic layer. The second conductive layer includes a plurality of first traces fully surrounded by the first and second magnetic layers. The package substrate includes a third conductive layer over the second magnetic layer. The magnetic materials may include manganese Mn ferrite materials, Zn/Mn ferrite materials, or Ni/Zn ferrite materials. The magnetic materials include material properties with a low constant value, a magnetic tangent value, a frequency, a base filler chemistry, a filler shape, a filler orientation, a filler percentage, a loading fraction value, a permeability, an insertion loss, and a resin formulation.
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公开(公告)号:US20240006323A1
公开(公告)日:2024-01-04
申请号:US17853018
申请日:2022-06-29
Applicant: Intel Corporation
Inventor: Lijiang Wang , Naren Sreenivas Viswanathan , Sujit Sharan , Jiwei Sun
IPC: H01L23/538 , H01L25/065
CPC classification number: H01L23/5381 , H01L23/5386 , H01L23/5383 , H01L25/0655
Abstract: An electronic device may include an interconnect bridge. The interconnect bridge may include a first electrical routing trace having a first routing length and a corresponding first transit time for a first electrical signal to transmit across the first routing length. The first electrical routing trace may transmit the first electrical signal along a major plane of the interconnect bridge between a first interconnect and a second interconnect. The interconnect bridge may include a routing trace deviation in communication with the first electrical routing trace. The routing trace deviation is outside a direct route between the first interconnect and the second interconnect. The routing trace deviation may alter one or more of capacitance or resistance of the first electrical routing trace and correspondingly alter the first routing time.
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公开(公告)号:US11715889B2
公开(公告)日:2023-08-01
申请号:US17402916
申请日:2021-08-16
Applicant: Intel Corporation
Inventor: Zhichao Zhang , Jiwei Sun , Kemal Aygun
CPC classification number: H01Q21/24 , H05K1/0243 , H05K1/0248 , H01P9/00 , H05K2201/10098
Abstract: Length matching and phase matching between circuit paths of differing lengths is disclosed. Two signals are specified to arrive at respective path destinations at a predetermined time and with a predetermined phase. An IC provides a first electronic signal over a first conductive path to a first destination and a second electronic signal over a second conductive path to a second destination. A first slow wave structure comprises the first conductive path and a second slow wave structure comprises the second conductive path. The effective relative permittivity of the first slow wave structure is tuned such that the first electronic signal arrives at its destination at a first time and at a first phase, and the effective relative permittivity of the second slow wave structure is tuned such that the second electronic signal arrives at its destination at a second time and at a second phase.
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