公开(公告)号：US10748842B2

公开(公告)日：2020-08-18

申请号：US15926531

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kaladhar Radhakrishnan ,  Kemal Aygun

IPC: H01L23/49 ,  H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US12242290B2

公开(公告)日：2025-03-04

申请号：US17484286

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  William J. Lambert ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini ,  Henning Braunisch ,  Stephen Morein ,  Aleksandar Aleksov ,  Feras Eid

IPC: G05F1/44 ,  H01L23/50 ,  H01L25/065

Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US12074514B2

公开(公告)日：2024-08-27

申请号：US17025745

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Kaladhar Radhakrishnan ,  Beomseok Choi ,  Michael Hill

IPC: H02M3/07 ,  H01L23/00 ,  H01L25/065 ,  H02M1/00

CPC classification number: H02M3/07 ,  H01L24/17 ,  H01L25/0655 ,  H01L2924/1427 ,  H02M1/0045 ,  H02M1/009

Abstract: Embodiments disclosed herein include two stage voltage regulators for electronic systems. In an embodiment, a voltage regulator comprises a switched capacitor voltage regulator (SCVR). In an embodiment, the SCVR receives a first voltage as an input and outputs a plurality of SCVR output voltages. In an embodiment, the voltage regulator further comprises a low-dropout (LDO) regulator. In an embodiment, the LDO regulator receives one or more of the plurality of SCVR output voltages as LDO input voltages, and where the LDO regulator outputs a second voltage.

公开(公告)号：US11916006B2

公开(公告)日：2024-02-27

申请号：US17822200

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/498 ,  G05F1/46 ,  H01L23/00 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F27/24

CPC classification number: H01L23/49838 ,  G05F1/46 ,  H01L23/5226 ,  H01L23/642 ,  H01L23/645 ,  H01L24/17 ,  H01L28/10 ,  H01L28/40 ,  H01F27/24

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

公开(公告)号：US11735535B2

公开(公告)日：2023-08-22

申请号：US16596328

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Kaladhar Radhakrishnan ,  Krishna Bharath ,  Clive Hendricks

IPC: H01L23/64 ,  H01F17/00 ,  H01F17/04 ,  H01F41/04 ,  H01F41/12 ,  H01F27/32 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/645 ,  H01F17/0006 ,  H01F17/04 ,  H01F27/32 ,  H01F41/041 ,  H01F41/12 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01F2017/0086 ,  H01L2224/16225 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: Embodiments include an inductor, a method to form the inductor, and a semiconductor package. An inductor includes a plurality of plated-through-hole (PTH) vias in a substrate layer, and a plurality of magnetic interconnects with a plurality of openings in the substrate layer. The openings of the magnetic interconnects surround the PTH vias. The inductor also includes an insulating layer in the substrate layer, a first conductive layer over the PTH vias, magnetic interconnects, and insulating layer, and a second conductive layer below the PTH vias, magnetic interconnects, and insulating layer. The insulating layer surrounds the PTH vias and magnetic interconnects. The magnetic interconnects may have a thickness substantially equal to a thickness of the PTH vias. The magnetic interconnects may be shaped as hollow cylindrical magnetic cores with magnetic materials. The magnetic materials may include ferroelectric, conductive, or epoxy materials. The hollow cylindrical magnetic cores may be ferroelectric cores.

公开(公告)号：US11682613B2

公开(公告)日：2023-06-20

申请号：US17360701

申请日：2021-06-28

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kaladhar Radhakrishnan ,  Kemal Aygun

IPC: H01L23/49 ,  H01L23/64 ,  H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/68 ,  H01L23/49827 ,  H01L24/17 ,  H01L23/5384 ,  H01L2224/08165 ,  H01L2224/16157 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24221 ,  H01L2224/32165 ,  H01L2224/32235 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2924/30111

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20230068300A1

公开(公告)日：2023-03-02

申请号：US17412724

申请日：2021-08-26

Applicant: INTEL CORPORATION

Inventor： Krishna Bharath ,  William J. Lambert ,  Christopher Schaef ,  Alexander Lyakhov ,  Kaladhar Radhakrishnan ,  Sriram Srinivasan

IPC: H01L25/16 ,  H01L23/31 ,  H01L49/02 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic assembly is provided, comprising a first IC die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR) electrically coupled to the first IC die, a package substrate having inductors of the VR electrically coupled to the first IC die and the second IC die, and a mold compound between the first IC die and the package substrate. The VR receives power at a first voltage from the package substrate and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the second IC die is in the mold compound. In some embodiments, the mold compound and the second IC die are comprised in a discrete interposer electrically coupled to the first IC die with die-to-die interconnects and to the package substrate with die-to-package substrate interconnects.

公开(公告)号：US11437294B2

公开(公告)日：2022-09-06

申请号：US16059513

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Amit Kumar Jain ,  Kaladhar Radhakrishnan ,  Jonathan P. Douglas ,  Chin Lee Kuan

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  G06F1/20

Abstract: Embodiments disclosed herein include electronics packages with improved thermal pathways. In an embodiment, an electronics package includes a package substrate. In an embodiment, the package substrate comprises a plurality of backside layers, a plurality of front-side layers, and a core layer between the plurality of backside layers and the plurality of front-side layers. In an embodiment, an inductor is embedded in the plurality of backside layers. In an embodiment, a plurality of bumps are formed over the front-side layers and thermally coupled to the inductor. In an embodiment, the plurality of bumps are thermally coupled to the core layer by a plurality of vias.

公开(公告)号：US11380652B2

公开(公告)日：2022-07-05

申请号：US16635501

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Beomseok Choi ,  Kaladhar Radhakrishnan ,  William Lambert ,  Michael Hill ,  Krishna Bharath

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00

Abstract: An apparatus is provided which comprises: a first set of one or more contacts on a first die surface, the first set of one or more contacts to couple with contacts of an integrated circuit die, one or more multi-level voltage clamps coupled with the first set of one or more contacts, the one or more multi-level voltage clamps switchable between two or more voltages, one or more integrated voltage regulators coupled with the one or more multi-level voltage clamps, the one or more integrated voltage regulators to provide an output voltage, one or more through silicon vias (TSVs) coupled with the one or more integrated voltage regulators, and a second set of one or more contacts on a second die surface, opposite the first die surface, the second set of one or more contacts coupled with the one or more TSVs, and the second set of one or more contacts to couple with contacts of a package substrate. Other embodiments are also disclosed and claimed.

公开(公告)号：US11215662B2

公开(公告)日：2022-01-04

申请号：US16020425

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： William Lambert ,  Kaladhar Radhakrishnan ,  Michael Hill

IPC: G01R31/28 ,  G05F1/46

Abstract: Techniques and mechanisms for mitigating damage to voltage regulator (VR) circuitry of a packaged device. In an embodiment, the VR circuitry comprises a circuit leg between a first node and a second node. During a burn-in process, the VR circuitry provides a regulated output voltage to a load circuit via the first node, wherein the output voltage is based on a supply voltage received via the second node. While the VR circuitry provides the regulated output voltage to the load circuit, a supply current is provided to the load circuit via a path which is independent of any leg which is between the first node and the second node. In another embodiment, an integrated circuit (IC) chip of the packaged device comprises the load circuit, and the leg further comprises an off-chip coil structure which is distinct from the IC chip.