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    LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS
    12.
    发明申请
    LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS 审中-公开
    逻辑芯片，包括嵌入式磁性隧道结

    公开(公告)号：WO2014142978A1

    公开(公告)日：2014-09-18

    申请号：PCT/US2013/032151

    申请日：2013-03-15

    Applicant: INTEL CORPORATION

    Inventor： LEE, Kevin J. ,  GHANI, Tahir ,  STEIGERWALD, Joseph M. ,  EPPLE, John H. ,  WANG, Yih

    IPC: G11C11/15 ,  H01L27/115 ,  H01L21/8247

    CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L27/226 ,  H01L43/08

    Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.

    Abstract translation: 实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上MTJ层，较低MTJ层和与上MTJ层和下MTJ层直接接触的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。 另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。 在一个实施例中，第一和第二ILD直接彼此接触。 本文描述了其它实施例。

    APPROACHES FOR EMBEDDING SPIN HALL MTJ DEVICES INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES
    13.
    发明申请
    APPROACHES FOR EMBEDDING SPIN HALL MTJ DEVICES INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES 审中-公开
    将SPIN HALL MTJ设备嵌入到逻辑处理器和结果结构中的方法

    公开(公告)号：WO2017155507A1

    公开(公告)日：2017-09-14

    申请号：PCT/US2016/021241

    申请日：2016-03-07

    Applicant: INTEL CORPORATION

    Inventor： LEE, Kevin J. ,  WANG, Yih

    IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/18 ,  H01L43/04 ,  H01L43/065 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14

    Abstract: Approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including fin-FET transistors disposed in a dielectric layer disposed above a substrate. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall electrode (2T1MTJ SHE) bit cells. The transistors of the 2T1MTJ SHE bit cells are fin-FET transistors disposed in the dielectric layer.

    Abstract translation: 描述了将自旋霍尔MTJ装置嵌入到逻辑处理器中的方法以及所得到的结构。 在一个示例中，逻辑处理器包括逻辑区域，该逻辑区域包括设置在设置在衬底上方的介电层中的鳍式-FET晶体管。 逻辑处理器还包括包括多个双晶体管一个磁隧道结（MTJ）自旋霍尔电极（2T1MTJ SHE）位单元的存储器阵列。 2T1MTJ SHE位单元的晶体管是位于介质层中的鳍式FET晶体管。

    DIELECTRIC BUFFER LAYER
    14.
    发明申请
    DIELECTRIC BUFFER LAYER 审中-公开
    介质缓冲层

    公开(公告)号：WO2017099736A1

    公开(公告)日：2017-06-15

    申请号：PCT/US2015/064620

    申请日：2015-12-09

    Applicant: INTEL CORPORATION

    Inventor： TELANG, Adwait ,  MUIRHEAD, John-Gerard ,  LEE, Kevin J. ,  PATTABHIRAMAN, Sriram ,  JEONG, James

    IPC: H01L21/768

    CPC classification number: H01L24/00 ,  H01L21/76837 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49894 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/5385 ,  H01L2224/16225

    Abstract: Embodiment of the present disclosure are directed to methods for forming an LMI landing pad on a silicon wafer. The method includes forming, on a substrate, a redistribution layer (RDL); forming, on the RDL and the substrate, a passivation layer covering the substrate and the RDL; forming, on the passivation layer, a patternable dielectric material layer; processing the patternable dielectric material layer to expose a portion of the passivation layer covering the RDL; processing the portion of the passivation layer covering the RDL to expose a portion of the RDL; and forming, on the exposed portion of the RDL, an LMI landing pad. The resulting wafer can include a redistribution line having a top portion and a sidewall portion; a passivation layer covering the sidewall portion; a dielectric layer covering the passivation layer; and a metal interface covering the top portion of the redistribution line.

    Abstract translation: 本公开的实施例针对用于在硅晶片上形成LMI着陆焊盘的方法。 该方法包括在衬底上形成再分布层（RDL）; 在所述RDL和所述衬底上形成覆盖所述衬底和所述RDL的钝化层; 在钝化层上形成可图案化的电介质材料层; 处理可图案化的介电材料层以暴露覆盖RDL的部分钝化层; 处理覆盖RDL的部分钝化层以暴露部分RDL; 以及在RDL的暴露部分上形成LMI着陆垫。 所得晶片可包括具有顶部和侧壁部分的再分布线; 覆盖所述侧壁部分的钝化层; 覆盖钝化层的介电层; 和一个覆盖再分配线顶部的金属接口。

    LANDING STRUCTURE FOR THROUGH-SILICON VIA
    17.
    发明申请
    LANDING STRUCTURE FOR THROUGH-SILICON VIA 审中-公开
    通过硅的接地结构

    公开(公告)号：WO2014100278A1

    公开(公告)日：2014-06-26

    申请号：PCT/US2013/076289

    申请日：2013-12-18

    Applicant: INTEL CORPORATION ,  PELTO, Christopher M. ,  BRAIN, Ruth A. ,  LEE, Kevin J. ,  LEATHERMAN, Gerald S.

    Inventor： PELTO, Christopher M. ,  BRAIN, Ruth A. ,  LEE, Kevin J. ,  LEATHERMAN, Gerald S.

    IPC: H01L23/48

    CPC classification number: H01L23/481 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/5226 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed

    Abstract translation: 本公开的实施例描述与使用互连层的互连结构形成用于穿硅通孔（TSV）的着陆结构相关联的技术和配置。 在实施例中，一种装置包括具有第一表面和与第一表面相对的第二表面的半导体衬底，设置在半导体衬底的第一表面上的器件层，器件层包括一个或多个晶体管器件，布置的互连层 在所述器件层上，所述互连层包括多个互连结构以及设置在所述第一表面和所述第二表面之间的一个或多个穿硅通孔，其中所述多个互连结构包括互连结构，所述互连结构与所述一个或多个 TSV并且被配置为提供一个或多个TSV的一个或多个相应的着陆结构。 可以描述和/或要求保护其他实施例

    INTEGRATED CIRCUIT DIE HAVING BACKSIDE PASSIVE COMPONENTS AND METHODS ASSOCIATED THEREWITH
    20.
    发明公开
    INTEGRATED CIRCUIT DIE HAVING BACKSIDE PASSIVE COMPONENTS AND METHODS ASSOCIATED THEREWITH 审中-公开
    具有背面被动元件的集成电路裸片及其相关方法

    公开(公告)号：EP3198637A1

    公开(公告)日：2017-08-02

    申请号：EP14902796.3

    申请日：2014-09-26

    Applicant: Intel Corporation

    Inventor： LEE, Kevin J.

    IPC: H01L23/48

    CPC classification number: H01L25/0652 ,  H01L23/145 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53252 ,  H01L25/50 ,  H01L28/40 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/15311

    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例针对集成电路（IC）管芯。 在实施例中，IC管芯可以包括半导体衬底，设置在半导体衬底的第一侧上的多个有源部件以及设置在半导体衬底的第二侧上的多个无源部件。 在实施例中，第二侧可以布置为与第一侧相对。 在一些实施例中，无源组件可以包括电容器和/或电阻器，而在一些实施例中，有源组件可以包括晶体管。 其他实施例可以被描述和/或要求保护。

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