公开(公告)号：US20210043572A1

公开(公告)日：2021-02-11

申请号：US17083177

申请日：2020-10-28

Applicant: Intel Corporation

Inventor： Mathew J. Manusharow ,  Jonathan Rosenfeld

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

公开(公告)号：US10453795B2

公开(公告)日：2019-10-22

申请号：US15773896

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos Zhang ,  Mathew J. Manusharow ,  Kemal Aygun ,  Mohiuddin Mazumder

IPC: H01L23/50 ,  H01R13/6471 ,  H05K1/02 ,  H01L23/528 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66

Abstract: A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.

公开(公告)号：US10186465B2

公开(公告)日：2019-01-22

申请号：US15748138

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel A. Elsherbini ,  Henning Braunisch ,  Yidnekachew S. Mekonnen ,  Krishna Bharath ,  Mathew J. Manusharow ,  Aleksandar Aleksov ,  Nathan Fritz

IPC: H01L23/14 ,  H01L23/12 ,  H01L23/473 ,  H01L21/48 ,  H01L23/538 ,  H01L23/492

Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.

公开(公告)号：US20170135211A1

公开(公告)日：2017-05-11

申请号：US14937047

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Mathew J. Manusharow

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/32 ,  H05K1/18 ,  H05K3/00

CPC classification number: H05K1/116 ,  H05K1/0234 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0047 ,  H05K3/32 ,  H05K3/4069 ,  H05K3/4084 ,  H05K3/4644 ,  H05K2201/0329 ,  H05K2201/0391 ,  H05K2201/0776 ,  H05K2201/09627 ,  H05K2201/10015 ,  H05K2203/14

Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.

公开(公告)号：US09633938B2

公开(公告)日：2017-04-25

申请号：US14866491

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Mathew J. Manusharow ,  Daniel N. Sobieski ,  Mihir K. Roy ,  William J. Lambert

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/02 ,  H01L21/32 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/285

CPC classification number: H01L23/49838 ,  H01L21/02263 ,  H01L21/28556 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/4857 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1205 ,  H05K1/162

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

公开(公告)号：US20160336223A1

公开(公告)日：2016-11-17

申请号：US15220143

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Harold Ryan Chase ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Mark Hlad

IPC: H01L21/768 ,  H01L23/36 ,  H01L21/288

CPC classification number: H01L21/76879 ,  H01L21/288 ,  H01L21/76838 ,  H01L23/00 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H05K1/0219 ,  H05K1/0222 ,  H05K3/4602 ,  H05K2201/09581 ,  H01L2924/014

Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

公开(公告)号：US20160204067A1

公开(公告)日：2016-07-14

申请号：US15056625

申请日：2016-02-29

Applicant: Intel Corporation

Inventor： Harold Ryan Chase ,  Mathew J. Manusharow ,  Mihir K. Roy

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L21/56 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/83005 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/18162 ,  H05K1/183 ,  H05K1/186 ,  H01L2924/00

Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.

公开(公告)号：US09214439B2

公开(公告)日：2015-12-15

申请号：US14293222

申请日：2014-06-02

Applicant: Intel Corporation

Inventor： Ravi K. Nalla ,  Mathew J. Manusharow

IPC: H01L21/20 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/34 ,  H01L21/768 ,  H01L23/36 ,  H01L23/48 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: H01L24/20 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24227 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H05K1/0209 ,  H05K1/185 ,  H05K3/4682

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，形成围绕管芯的电介质材料，在电介质材料中形成堆积层，以形成无芯无阻堆积的封装结构，以及图案化载体材料以在封装结构上形成微通道结构。

公开(公告)号：US20150011050A1

公开(公告)日：2015-01-08

申请号：US14495396

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及可嵌入封装组件中的桥互连组件的技术和配置。 在一个实施例中，包装组件包括被配置为在第一管芯和第二管芯之间布置电信号的封装衬底和嵌入在封装衬底中并被配置为在第一管芯和第二管芯之间布置电信号的桥， 包括桥接基板，通过桥接基板形成的一个或多个通孔通孔（THV）和布置在桥接基板的表面上的一个或多个走线，以在第一管芯和第二管芯之间布置电信号。 包括迹线和桥互连组件的接地平面的布线特征可以由气隙分开。 可以描述和/或要求保护其他实施例。

公开(公告)号：US12094827B2

公开(公告)日：2024-09-17

申请号：US18216989

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Mathew J. Manusharow ,  Jonathan Rosenfeld

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/647 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/50 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.