公开(公告)号：US11443970B2

公开(公告)日：2022-09-13

申请号：US16803361

申请日：2020-02-27

Applicant: Intel Corporation

Inventor： Manohar S. Konchady ,  Tao Wu ,  Mihir K. Roy ,  Wei-Lun K. Jen ,  Yi Li

IPC: H01L21/683 ,  H01L23/538 ,  H01L23/498

Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

公开(公告)号：US20220028790A1

公开(公告)日：2022-01-27

申请号：US17494404

申请日：2021-10-05

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L25/065 ,  H01L25/18

Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

公开(公告)号：US10971416B2

公开(公告)日：2021-04-06

申请号：US16526497

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Mihir K. Roy ,  Aleksandar Aleksov ,  Yidnekachew S. Mekonnen ,  Javier Soto Gonzalez ,  Feras Eid ,  Suddhasattwa Nad ,  Meizi Jiao

IPC: H01L23/52 ,  H01L23/12 ,  H01L23/48 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US09917044B2

公开(公告)日：2018-03-13

申请号：US15028278

申请日：2015-05-13

Applicant: INTEL CORPORATION

Inventor： Zheng Zhou ,  Mihir K. Roy ,  Chong Zhang ,  Kyu-Oh Lee ,  Amanda E. Schuckman

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76804 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/14 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.

公开(公告)号：US09820390B2

公开(公告)日：2017-11-14

申请号：US14566208

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Islam A. Salama ,  Yonggang Li

IPC: H05K3/22 ,  H05K3/42 ,  H01L23/498 ,  G06F1/18 ,  H01L23/492

CPC classification number: H05K3/422 ,  G06F1/183 ,  H01L23/492 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.

公开(公告)号：US09496209B2

公开(公告)日：2016-11-15

申请号：US14992535

申请日：2016-01-11

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/14 ,  H01L23/538 ,  H01L21/48 ,  H05K1/03 ,  H05K1/14 ,  H05K3/46 ,  H01L23/00 ,  H05K1/18

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US09355952B2

公开(公告)日：2016-05-31

申请号：US14798395

申请日：2015-07-13

Applicant: Intel Corporation

Inventor： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L21/44 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/50 ,  H05K1/11 ,  H05K3/10 ,  H05K3/42 ,  H01L21/56 ,  H05K3/34

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

公开(公告)号：US20190019755A1

公开(公告)日：2019-01-17

申请号：US16135695

申请日：2018-09-19

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H05K1/03 ,  H05K1/14 ,  H05K1/18 ,  H05K3/46

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US20170125349A1

公开(公告)日：2017-05-04

申请号：US15350393

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L21/683 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US09633938B2

公开(公告)日：2017-04-25

申请号：US14866491

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Mathew J. Manusharow ,  Daniel N. Sobieski ,  Mihir K. Roy ,  William J. Lambert

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/02 ,  H01L21/32 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/285

CPC classification number: H01L23/49838 ,  H01L21/02263 ,  H01L21/28556 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/4857 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1205 ,  H05K1/162

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).