公开(公告)号：US11804523B2

公开(公告)日：2023-10-31

申请号：US16580941

申请日：2019-09-24

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Anand S. Murthy ,  Nicholas G. Minutillo ,  Suresh Vishwanath ,  Mohammad Hasan ,  Biswajeet Guha ,  Subrina Rafique

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/785

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20230282701A1

公开(公告)日：2023-09-07

申请号：US17687045

申请日：2022-03-04

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Shengsi Liu ,  Robert Joachim ,  Mohammad Hasan ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/0886

Abstract: Techniques are provided herein to form semiconductor devices having gate cut structures. Adjacent semiconductor devices having semiconductor regions (e.g., fins or nanoribbons) extending in a first direction have a gate structure that extends over the semiconductor regions in a second direction and are separated by a gate cut structure extending in the first direction and interrupting the gate structure. The gate cut structure further extends between adjacent source or drain regions (corresponding to the adjacent semiconductor devices). A dielectric liner on at least a sidewall and/or top surface of the source or drain regions and also extends up a sidewall surface of the gate cut structure. In some cases, the gate structure includes a gate dielectric present on the semiconductor regions, but not present on the gate cut structure. A contact may pass through the liner and at least partially land on a source or drain region.

公开(公告)号：US20230275124A1

公开(公告)日：2023-08-31

申请号：US17681263

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Gilbert Dewey ,  Saurabh Morarka ,  Sikandar Abbas ,  Mohammad Hasan

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/088

Abstract: Techniques are provided herein to form semiconductor devices having epitaxial diffusion regions (e.g., source and/or drain regions) wrapped by a conductive contact. In an example, a semiconductor device includes a source or drain region and a conductive layer that extends around the source or drain region such that the conductive layer at least contacts the sidewalls of the source or drain region or wraps completely around the source or drain region. In some examples, a conducive contact extends upward through a thickness of an adjacent dielectric layer and contacts the conductive layer from below, thus forming a backside contact. By forming a conductive layer around multiple sides of the source or drain region (rather than just contacting a top or bottom surface) more surface area of the source or drain region is contacted thus providing an improved ohmic contact and a lower overall contact resistance.

公开(公告)号：US20230088753A1

公开(公告)日：2023-03-23

申请号：US17482870

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Stephen M. Cea ,  Aaron D. Lilak ,  Patrick Keys ,  Cory Weber ,  Rishabh Mehandru ,  Anand S. Murthy ,  Biswajeet Guha ,  Mohammad Hasan ,  William Hsu ,  Tahir Ghani ,  Chang Wan Han ,  Kihoon Park ,  Sabih Omar

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/74 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

公开(公告)号：US20220199797A1

公开(公告)日：2022-06-23

申请号：US17131467

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Willy Rachmady ,  Hsin-Fen Li ,  Christopher Parker ,  Prashant Wadhwa ,  Tahir Ghani ,  Mohammad Hasan ,  Jianqiang Lin

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L27/088

Abstract: A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.