公开(公告)号：WO2018053750A1

公开(公告)日：2018-03-29

申请号：PCT/CN2016/099714

申请日：2016-09-22

Applicant: INTEL CORPORATION ,  GUO, Mao ,  KIM, Hyoung Il ,  SHE, Yong ,  GOGINENI, Sireesha

Inventor： GUO, Mao ,  KIM, Hyoung Il ,  SHE, Yong ,  GOGINENI, Sireesha

IPC: H01L23/28

Abstract: Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

Abstract translation: 本文公开了与集成电路（IC）封装设计相关联的设备，系统和方法。 在实施例中，IC封装可以包括第一管芯和第二管芯。 IC封装可以包括位于第一管芯和第二管芯之间的间隔物，间隔物包括玻璃以及至少部分地包围第一管芯，第二管芯和间隔物的模塑料。 其他实施例可以被描述和/或要求保护。

公开(公告)号：WO2016074176A1

公开(公告)日：2016-05-19

申请号：PCT/CN2014/090939

申请日：2014-11-12

Applicant: INTEL CORPORATION ,  TANG, Jiamiao ,  ZHAO, Junfeng ,  SKINNER, Michael P. ,  SHE, Yong ,  SIR, Jiun Hann ,  CHEAH, Bok Eng ,  PERIAMAN, Shanggar ,  OOI, Kooi Chi ,  CHEW, Yen Hsiang

Inventor： TANG, Jiamiao ,  ZHAO, Junfeng ,  SKINNER, Michael P. ,  SHE, Yong ,  SIR, Jiun Hann ,  CHEAH, Bok Eng ,  PERIAMAN, Shanggar ,  OOI, Kooi Chi ,  CHEW, Yen Hsiang

IPC: H01L23/28

CPC classification number: G06F1/163 ,  A41B1/00 ,  A41D1/06 ,  A41D1/08 ,  A41F9/002 ,  A43B3/001 ,  A43B3/0015 ,  A43B7/141 ,  A44C5/0015 ,  A44C15/005 ,  F03G5/06 ,  G06F1/189 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/181 ,  H02J1/14 ,  H05K1/189 ,  H05K2201/05 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate (102). The flexible substrate (102) may have a plurality of dies (104 -112) coupled therewith. The IC package may include a first encapsulation material (116-120), having a first rigidity, disposed on the flexible substrate (102) to at least partially encapsulate each die of the plurality dies (104 -112). The IC package may further include a second encapsulation material (122), having a second rigidity, disposed on the flexible substrate (102). In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及集成电路（IC）封装。 在实施例中，集成电路（IC）封装可以包括柔性基板（102）。 柔性基板（102）可以具有与其连接的多个管芯（104-112）。 IC封装可以包括具有第一刚性的第一封装材料（116-120），其设置在柔性基板（102）上以至少部分地封装多个管芯（104-112）中的每个管芯。 IC封装还可以包括设置在柔性基板（102）上的具有第二刚性的第二封装材料（122）。 在实施例中，第二刚性和第一刚度彼此不同。 可以描述和/或要求保护其他实施例。

公开(公告)号：WO2019061166A1

公开(公告)日：2019-04-04

申请号：PCT/CN2017/104029

申请日：2017-09-28

Applicant: INTEL CORPORATION ,  XU, Zhijun ,  LIU, Bin ,  SHE, Yong ,  DING, Zhicheng

Inventor： XU, Zhijun ,  LIU, Bin ,  SHE, Yong ,  DING, Zhicheng

IPC: H01L25/00 ,  H01L23/13

Abstract: An apparatus, comprising an IC package having a first surface, a second surface opposing the first surface, and at least four sidewalls extending orthogonally from a perimeter of the first surface to a perimeter of the second surface, and one or more electronic devices disposed on one or more of the at least four sidewalls.

公开(公告)号：WO2018119782A1

公开(公告)日：2018-07-05

申请号：PCT/CN2016/112717

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： TAN, Aiping ,  LIU, Bin ,  DENG, Li ,  SHE, Yong ,  DING, Zhicheng ,  GUO, Mao

IPC: H01L23/31 ,  H01L25/00 ,  H01L21/52

Abstract: Techniques for providing an integrated circuit package that avoids or eliminates x-y area and z-height compared to conventional integrated circuit packages. In certain examples, an example package can utilize a substrate with an opening and bottom side or sidewall terminations to avoid adding addition x-y substrate area or z-axis package height associated with an integrated circuit die of a stack of integrated circuit dies of the package.

公开(公告)号：WO2018058416A1

公开(公告)日：2018-04-05

申请号：PCT/CN2016/100760

申请日：2016-09-29

Applicant: INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

Inventor： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

IPC: H01L23/522

Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.

Abstract translation:

预先封装的阶梯式堆叠内存模块安装在至少有一个附加组件的电路板上。 楼梯堆叠的存储器模块包括相对于处理器裸片垂直堆叠的多个存储器裸片。 邻近处理器芯片使用垫片为阶梯堆叠的内存模块创建桥接。 楼梯式堆叠存储器模块中的每个存储器裸片包括从矩阵中露出的用于连接的垂直接合线。 矩阵包围阶梯堆叠的存储器模块和处理器裸片的至少一部分。 矩阵也可能包含至少一个附加组件。

公开(公告)号：WO2017166308A1

公开(公告)日：2017-10-05

申请号：PCT/CN2016/078363

申请日：2016-04-01

Applicant: INTEL CORPORATION ,  SHE, Yong

Inventor： SHE, Yong

IPC: H01L23/48 ,  H01L21/60

Abstract: Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag).

Abstract translation:

提供与集成电路互连的技术和机制。 在一个实施例中，封装器件包括衬底和一个或多个集成电路（IC）管芯。 第一导电焊盘形成在第一IC管芯的第一侧，并且第二导电焊盘形成在衬底或另一IC管芯的第二侧。 引线键合在第一导电垫和第二导电垫之间连接导线，其中导线的远端经由凸块键合到第一导电垫和第二导电垫的邻接的一个。 小于导线硬度的凸块线束可减轻由于导线接合应力而可能发生的相邻焊盘的​​损坏。 在另一个实施例中，导线包括铜（Cu）并且凸块包括金（Au）或银（Ag）。

公开(公告)号：WO2017101037A1

公开(公告)日：2017-06-22

申请号：PCT/CN2015/097545

申请日：2015-12-16

Applicant: INTEL CORPORATION ,  GUO, Mao ,  MEYERS, John ,  SHE, Yong ,  LIU, Bin ,  TAN, Lingyan L.

Inventor： GUO, Mao ,  MEYERS, John ,  SHE, Yong ,  LIU, Bin ,  TAN, Lingyan L.

IPC: H01L27/06 ,  H01L23/02

CPC classification number: H01L23/02 ,  H01L23/3128 ,  H01L25/065 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A system in package and method of making as system in package are disclosed. The system in package has a substrate(102) with a plurality of passive devices(104) mounted thereon. A molding compound(106) envelopes the plurality of passive devices(104) to define a flat surface(116) substantially parallel to a surface of the substrate(102). A plurality of integrated circuit dies(110) is coupled successively to the flat surface(116).

Abstract translation: 披露了封装中的系统和封装中系统的制造方法。 封装中的系统具有其上安装有多个无源器件（104）的衬底（102）。 模制化合物（106）包封多个无源器件（104）以限定基本平行于衬底（102）的表面的平坦表面（116）。 多个集成电路管芯（110）连续地耦合到平坦表面（116）。

公开(公告)号：WO2017049585A1

公开(公告)日：2017-03-30

申请号：PCT/CN2015/090716

申请日：2015-09-25

Applicant: INTEL CORPORATION ,  SHE, Yong ,  MEYERS, John G. ,  DING, Zhicheng ,  PATTEN, Richard

Inventor： SHE, Yong ,  MEYERS, John G. ,  DING, Zhicheng ,  PATTEN, Richard

IPC: H01L25/065 ,  H01L23/488

CPC classification number: H01L23/488 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83007 ,  H01L2224/92174 ,  H01L2224/92244 ,  H01L2924/14 ,  H01L2924/18162

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

Abstract translation: 互连堆叠集成电路（IC）裸片的技术和机制。 在一个实施例中，线的第一端耦合到堆叠的第一IC芯片，其中线的第二端进一步锚定到堆叠，而与耦合的第一端无关。 随后将包装材料设置在堆叠的IC管芯周围，并且包括第一端的电线的第一部分。 将电线的两点锚定到堆叠有助于提供机械支撑以阻止运动，否则在包装材料沉积时可能使电线移动和/或变形。 在另一个实施例中，导线的第一部分与导线的其余部分分离，再分布层耦合到第一部分，以实现第一IC裸片与叠层的另一IC芯片之间的互连。

公开(公告)号：EP3462488A1

公开(公告)日：2019-04-03

申请号：EP18191337.7

申请日：2018-08-28

Applicant: INTEL Corporation

Inventor： XU, Yi ,  PON, Florence ,  SHE, Yong

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.

公开(公告)号：EP3218928A1

公开(公告)日：2017-09-20

申请号：EP14889185.6

申请日：2014-11-12

Applicant: Intel Corporation

Inventor： TANG, Jiamiao ,  ZHAO, Junfeng ,  SKINNER, Michael P. ,  SHE, Yong ,  SIR, Jiun Hann ,  CHEAH, Bok Eng ,  PERIAMAN, Shanggar ,  OOI, Kooi Chi ,  CHEW, Yen Hsiang

IPC: H01L23/28

CPC classification number: G06F1/163 ,  A41B1/00 ,  A41D1/06 ,  A41D1/08 ,  A41F9/002 ,  A43B3/001 ,  A43B3/0015 ,  A43B7/141 ,  A44C5/0015 ,  A44C15/005 ,  F03G5/06 ,  G06F1/189 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/181 ,  H02J1/14 ,  H05K1/189 ,  H05K2201/05 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate (102). The flexible substrate (102) may have a plurality of dies (104 -112) coupled therewith. The IC package may include a first encapsulation material (116-120), having a first rigidity, disposed on the flexible substrate (102) to at least partially encapsulate each die of the plurality dies (104 -112). The IC package may further include a second encapsulation material (122), having a second rigidity, disposed on the flexible substrate (102). In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例针对集成电路（IC）封装。 在实施例中，集成电路（IC）封装可以包括柔性衬底。 柔性衬底可以具有与其耦合的多个管芯。 IC封装可以包括具有第一刚性的第一封装材料，该第一封装材料设置在柔性衬底上以至少部分地封装多个管芯中的每个管芯。 IC封装可以进一步包括设置在柔性基板上的具有第二刚性的第二封装材料。 在实施例中，第二刚性和第一刚性彼此不同。 其他实施例可以被描述和/或要求保护。