公开(公告)号：CA2883547A1

公开(公告)日：2015-09-06

申请号：CA2883547

申请日：2015-03-03

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： PARK SUNG-IK ,  KWON SUN-HYOUNG ,  LEE JAE-YOUNG ,  KIM HEUNG-MOOK ,  HUR NAM-HO

IPC: H03M13/11 ,  H03M13/27

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

公开(公告)号：CA2882457A1

公开(公告)日：2015-08-20

申请号：CA2882457

申请日：2015-02-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： PARK SUNG-IK ,  KWON SUN-HYOUNG ,  LEE JAE-YOUNG ,  KIM HEUNG-MOOK ,  HUR NAM-HO

IPC: H03M13/11 ,  H03M13/27 ,  H04L1/24 ,  H04L27/36

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

公开(公告)号：CA2864718A1

公开(公告)日：2016-02-14

申请号：CA2864718

申请日：2014-09-25

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： PARK SUNG-IK ,  KIM HEUNG-MOOK ,  KWON SUN-HYOUNG ,  HUR NAM-HO

IPC: H03M13/11 ,  H04N19/90

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

公开(公告)号：CA2864694A1

公开(公告)日：2016-02-14

申请号：CA2864694

申请日：2014-09-25

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： PARK SUNG-IK ,  KWON SUN-HYOUNG ,  HUR NAM-HO ,  KIM HEUNG-MOOK

IPC: H04L1/22 ,  H04L1/24 ,  H04N19/89 ,  H04W80/02

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

公开(公告)号：CA2892103A1

公开(公告)日：2015-11-22

申请号：CA2892103

申请日：2015-05-21

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： PARK SUNG-IK ,  KWON SUN-HYOUNG ,  LIM BO-MI ,  LEE JAE-YOUNG ,  KIM HEUNG-MOOK ,  HUR NAM-HO

IPC: H03M13/11 ,  H03M13/27 ,  H04L1/00 ,  H04L27/34

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

公开(公告)号：MX2015001936A

公开(公告)日：2015-10-26

申请号：MX2015001936

申请日：2015-02-12

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： PARK SUNG-IK ,  KIM HEUNG-MOOK ,  KWON SUN-HYOUNG ,  HUR NAM-HO ,  LEE JAE-YOUNG

IPC: H04N19/36

Abstract: Se divulgan un modulador y un método de modulación que usan una constelación de señal de 16 símbolos no uniforme; el modulador incluye una memoria y un procesador; la memoria recibe una palabra código que corresponde con un código de verificación de paridad de baja densidad (LDPC) que tiene una tasa de código de 7/15; el procesador mapea la palabra código a 16 símbolos de la constelación de señal de 16 símbolos no uniforme sobre una base de 4 bits.

公开(公告)号：MX2014012121A

公开(公告)日：2015-08-19

申请号：MX2014012121

申请日：2014-10-07

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： PARK SUNG-IK ,  KIM HEUNG-MOOK ,  KWON SUN-HYOUNG ,  HUR NAM-HO

IPC: H03M13/11 ,  G06F11/10

Abstract: Se describe un codificador de revisión de paridad de baja densidad (LDPC), un decodificador de LDPC y un método codificador de LDPC; el codificador de LDPC incluye una primera memoria, una segunda memoria y un procesador; la primera memoria almacena una palabra código de LDPC que tiene una longitud de 64800 y un índice de código de 7/15; la segunda memoria es inicializada a 0; el procesador genera la palabra código de LDPC que corresponde a los bits de información al realizar acumulación con respecto a la segunda memoria al usar una secuencia que corresponde a una matriz de revisión de paridad (PCM).

公开(公告)号：CA2881540A1

公开(公告)日：2015-08-13

申请号：CA2881540

申请日：2015-02-11

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： PARK SUNG-IK ,  KWON SUN-HYOUNG ,  LEE JAE-YOUNG ,  KIM HEUNG-MOOK ,  HUR NAM-HO

IPC: H03M13/11 ,  H03M13/27 ,  H03M13/31 ,  H04L1/24 ,  H04L27/34

Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

公开(公告)号：CA2881538A1

公开(公告)日：2015-08-13

申请号：CA2881538

申请日：2015-02-11

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： PARK SUNG-IK ,  KWON SUN-HYOUNG ,  LEE JAE-YOUNG ,  KIM HEUNG-MOOK ,  HUR NAM-HO

IPC: H03M13/11 ,  H03M13/27 ,  H03M13/31 ,  H04L1/24 ,  H04L27/34

Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

公开(公告)号：CA2864650A1

公开(公告)日：2016-02-14

申请号：CA2864650

申请日：2014-09-25

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： PARK SUNG-IK ,  KIM HEUNG-MOOK ,  KWON SUN-HYOUNG ,  HUR NAM-HO

IPC: H03M13/11 ,  H04N19/90

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).