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    11.
    发明专利
    未知

    公开(公告)号：FR2838868B1

    公开(公告)日：2005-06-03

    申请号：FR0204782

    申请日：2002-04-17

    Applicant: MEMSCAP

    Inventor： GIRARDIE LIONEL

    IPC: C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/28 ,  H01L21/316 ,  H01L29/51 ,  H01L29/92 ,  H01G4/002 ,  G11C11/401

    Abstract: A multilayer structure with strong relative permittivity is made up of a number of distinct layers each with a thickness of less than 500 Angstrom and made from a base of hafnium dioxide, zirconium dioxide and alumina. The hafnium dioxide, zirconium dioxide and alumina are formed from alloys with the formula HfxZrtAly)z and their stoichiometry varies from layer to layer. The structure is made up of at least five layers and at least one of the outer layers is made up of alumina. The layers are deposited by atomic layer deposition.

    12.
    发明专利
    未知

    公开(公告)号：FR2837622B1

    公开(公告)日：2005-03-25

    申请号：FR0203442

    申请日：2002-03-20

    Applicant: MEMSCAP

    Inventor： GIRARDIE LIONEL

    IPC: C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/28 ,  H01L21/316 ,  H01L29/51 ,  H01L29/92 ,  H01G4/002

    Abstract: A multilayer structure with strong relative permittivity is made up of a number of distinct layers each with a thickness of less than 500 Angstrom and made from a base of hafnium dioxide, zirconium dioxide and alumina. The hafnium dioxide, zirconium dioxide and alumina are formed from alloys with the formula HfxZrtAly)z and their stoichiometry varies from layer to layer. The structure is made up of at least five layers and at least one of the outer layers is made up of alumina. The layers are deposited by atomic layer deposition.

    COMPOSANT ELECTRONIQUE INCORPORANT UN CIRCUIT INTEGRE ET UN MICRO-CONDENSATEUR PLANAIRE
    16.
    发明专利
    COMPOSANT ELECTRONIQUE INCORPORANT UN CIRCUIT INTEGRE ET UN MICRO-CONDENSATEUR PLANAIRE 未知

    公开(公告)号：CA2414400A1

    公开(公告)日：2003-06-30

    申请号：CA2414400

    申请日：2002-12-10

    Applicant: MEMSCAP

    Inventor： GIRARDIE LIONEL

    IPC: H01L27/04 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/28 ,  H01L21/316 ,  H01L21/822 ,  H01L29/51 ,  H01L49/00 ,  H01G4/33 ,  H01L27/00 ,  H01L29/94

    Abstract: Composant électronique incorporant un circuit intégré réalisé dans un substrat (1) et un condensateur planaire, caractérisé en ce que le condensateur est réalisé au- dessus d'un niveau de métallisation du composant, ce niveau de métallisation formant une première électrode (2) de la capacité, et en ce que le condensateur comporte ~ une première couche (5) barrière à diffusion de l'oxygène, déposée au- dessus du niveau de métallisation (2); ~ un empilement (6) de plusieurs couches d'oxydes différents, chaque couche présentant une épaisseur inférieure à 100 nanomètres, l'empilement étant déposé au-dessus de la première couche barrière (5); ~ une seconde couche (7) barrière à la diffusion de l'oxygène déposée au- dessus de l'empilement (6) des couches d'oxydes; ~ une électrode métallique (20) présente au-dessus de la seconde couche barrière (7).

    17.
    发明专利
    未知

    公开(公告)号：FR2833411A1

    公开(公告)日：2003-06-13

    申请号：FR0115960

    申请日：2001-12-11

    Applicant: MEMSCAP

    Inventor： GIRARDIE LIONEL ,  DAVID JEAN BAPTISTE

    IPC: H01F17/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/08 ,  H01L49/00

    Abstract: An electronic component is fabricated by: (a) incorporating an inductive microcomponent comprising stack(s) of layer of material (10a) having a low relative permittivity; (b) depositing an upper resin layer; (c) etching the resin layer to form channels defining the turns; (d) depositing a copper diffusion barrier layer; and (e) planarizing until the upper resin layer is revealed. Fabrication of an electronic component, incorporating an inductive microcomponent placed on top of a substrate and connected by a metal contact(s), comprises: (a) depositing on the substrate a stack(s) of layer of material having a low relative permittivity and a layer forming a hard mask (12a); (b) making an aperture in the hard mask layer placed in the upper position, vertically in line with the metal contacts; (c) etching the layers of material having a low relative permittivity and the subjacent hard mask layers down to the metal contact to form a via; (d) depositing a layer forming a copper diffusion barrier; (e) depositing a copper initiating layer; (f) depositing, electrolytically, a copper layer filling the via and covering the initiating layer; (g) planarizing the upper face until the upper hard mask layer is exposed; (h) depositing an upper resin layer formed from a material having a low relative permittivity; (i) etching the resin layer to form channels defining the turns of the inductive microcomponent and of possible other conductive features; (j) depositing a copper diffusion barrier layer; (k) depositing a copper initiating layer; (l) depositing electrolytically on the channels; and (m) planarizing until the upper resin layer is revealed.

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