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公开(公告)号：DE69616462D1
公开(公告)日：2001-12-06
申请号：DE69616462
申请日：1996-08-22
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C , RIEDEL KLAUS R
Abstract: A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor (3). A debug module (10) of data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal. The DDATA signal provides data which reflects operand values and the PST signal provides encoded status information which reflects an execution status of a central processing unit 92). Furthermore, the DDATA signal also provides captured instruction address program flow changes to allow external development system (7) to trace an exact program flow without requiring an externally visible address bus or an externally visible data bus.
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公开(公告)号：DE69616917T2
公开(公告)日：2002-06-06
申请号：DE69616917
申请日：1996-08-22
Applicant: MOTOROLA INC
Inventor： HOHL WILLIAM A , CIRCELLO JOSEPH C
Abstract: A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unte (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).
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公开(公告)号：DE69616917D1
公开(公告)日：2001-12-20
申请号：DE69616917
申请日：1996-08-22
Applicant: MOTOROLA INC
Inventor： HOHL WILLIAM A , CIRCELLO JOSEPH C
Abstract: A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unte (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).
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公开(公告)号：IE970147A1
公开(公告)日：1997-10-08
申请号：IE970147
申请日：1997-03-03
Applicant: MOTOROLA INC
Inventor： CIRCELLO JOSEPH C , GAY JAMES G , GLOVER CLINTON T , TRAYNOR KEVIN M
Abstract: A system bus controller (103) within a processor (101) includes programmable logic for different modes of chip enable signals on a per-address-space basis. This allows for a "glueless" interface (107) between the processor (101) and different types of external devices (111, 112,113), such as memory devices. A chip select register value 604, 608, 612 is preprogrammed with respect to each external device coupled to the processor (101). This preprogrammed register value 604, 608, 612 is used by the system bus controller (103) to uniquely configure a read/write access signal to be sent to each of the external devices (111,112,113). .
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