公开(公告)号：WO2003005622A3

公开(公告)日：2003-01-16

申请号：PCT/US2002/020853

申请日：2002-07-02

Applicant: MOTOROLA, INC.

Inventor： MARTIN, Frederick, L. ,  STENGEL, Robert, E. ,  BAUTISTA, Edwin, E.

IPC: H04L27/36

Abstract: Phase shift key modulators (100, 500, 1000, 1400, 1700) are provided in which a multiphase signal source (108, 1402, 1406-1412,1702) is used to generate a plurality of phases of a carrier signal. A selector (110) is used to select one phase or a sequence of phases of the carrier signal to represent each bit pattern that is received from a binary data source (102, 1422). The multiphase signal source preferably comprises a multiphase oscillator that includes a phase locked ring of variable propagation delay inverters (202). Preferably, a phase sequencer (502) is used to select a monotonic sequence of phases to represent each bit pattern. Preferably two phase selectors (110, 1004) are used to simultaneously select two phases of carrier signal, and a phase interpolator (1106) is used to generate a sequence of phases from the two phases selected by the two phase selectors (110, 1004).

公开(公告)号：WO1994021038A1

公开(公告)日：1994-09-15

申请号：PCT/US1994002005

申请日：1994-02-18

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  BOCKELMAN, David, E. ,  STENGEL, Robert, E. ,  CORNETT, Kenneth, D.

IPC: H03H07/00

CPC classification number: H03H7/06

Abstract: An electronic circuit (300) includes first (302) and second (304) variable impedance devices coupled together. The fist (302) and second (304) variable impedance devices are designed such that each exhibits a transfer function which is substantially inverse with respect to the other about the operating point of the electronic circuit. This provides for an electronic circuit which exhibits verly low distortion characteristics. Circuits such as tunable filters, voltage-controlled oscillators (VCOs), receivers, etc. will benefit from using an electronic circuit (300) which exhibits such low distortion characteristics.

Abstract translation: 电子电路（300）包括耦合在一起的第一（302）和第二（304）可变阻抗器件。 第一（302）和第二（304）可变阻抗装置被设计成使得每个展现出相对于另一个关于电子电路的工作点基本上相反的传递函数。 这提供了显示出非常低的失真特性的电子电路。 诸如可调谐滤波器，压控振荡器（VCO），接收器等的电路将受益于使用具有这种低失真特性的电子电路（300）。

公开(公告)号：WO1990013188A1

公开(公告)日：1990-11-01

申请号：PCT/US1990001830

申请日：1990-04-09

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  STENGEL, Robert, E. ,  MARKO, Paul, David

IPC: H04B15/00

CPC classification number: H04B1/10

Abstract: A receiver (10) is provided where an information signal (11) is received (12) and examined to determine (20) its signal strength. When the signal strength is at least equal to a threshold, an unmodulated signal (40) is added to the received signal to improve the sensitivity of the receiver.

Abstract translation: 提供接收机（10），其中接收信息信号（11）（12）并进行检查以确定（20）其信号强度。 当信号强度至少等于阈值时，将未调制信号（40）加到接收信号上以提高接收机的灵敏度。

公开(公告)号：EP1810438A2

公开(公告)日：2007-07-25

申请号：EP05810355.7

申请日：2005-10-21

Applicant: Motorola, Inc.

Inventor： CAFARO, Nicholas, G. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

IPC: H04L7/00

CPC classification number: H04L7/0083 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00286 ,  H03L7/0812 ,  H04L7/0337

Abstract: A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

公开(公告)号：EP0569486B1

公开(公告)日：2000-11-08

申请号：EP92904869.2

申请日：1991-12-24

Applicant: MOTOROLA INC.

Inventor： STENGEL, Robert, E. ,  DAVENPORT, Roger, A.

IPC: H04B7/02 ,  H04B7/005

CPC classification number: H04W52/146 ,  H04W52/245 ,  H04W52/248

Abstract: The transmit power of a subscriber unit (106) operating in a communication system (100) is adjusted by a value which corresponds to the measured noise characteristic of a received signal at a receiving site (104).

公开(公告)号：EP0888675A1

公开(公告)日：1999-01-07

申请号：EP97921090.0

申请日：1997-04-02

Applicant: MOTOROLA, INC.

Inventor： O'DEA, Robert, J. ,  STENGEL, Robert, E.

IPC: H04L27

CPC classification number: H04L27/2032 ,  H04L27/368

Abstract: A modulated signal, having a varying magnitude signal envelope, is conditioned, such as to facilitate amplification (500). Minimum values are determined values for portions of the signal envelope (520, 530), and a window expansion function applied to scale each portion of the signal envelope having a minimum value below a particular threshold, such that each scaled portion has a new minimum value of at least the particular threshold (535, 540, 550, 555).

公开(公告)号：EP0554386A1

公开(公告)日：1993-08-11

申请号：EP91920601.0

申请日：1991-10-10

Applicant: MOTOROLA, INC.

Inventor： STENGEL, Robert, E.

IPC: H04B1 ,  H04B7

CPC classification number: H04W52/0229 ,  Y02D70/00

Abstract: A receiver 100 used for recovering modulation signals modulated on a carrier signal is disclosed. The receiver 100 includes a detector 204 and a decoder 206 for detecting the presence of a non-valid coded squelch signal and decoding such signal in the recovered modulation signal. The receiver 100 further includes a synchronizer 208 for synchronizing the detected non-valid coded signal. Receiver 100 is placed in a battery saver mode when a non-valid coded squelch signal is detected. The battery saver mode includes monitoring the recovered modulation signal for a change in the non-valid coded squelch signal. The battery saver mode is departed once a change in the non-valid coded squelch signal is detected.

公开(公告)号：WO2004114091A2

公开(公告)日：2004-12-29

申请号：PCT/US2004/019788

申请日：2004-06-18

Applicant: MOTOROLA, INC. ,  CAFARO, Nicholas, G. ,  STENGEL, Robert, E.

Inventor： CAFARO, Nicholas, G. ,  STENGEL, Robert, E.

IPC: G06F

CPC classification number: H03L7/0812 ,  G06F1/06

Abstract: A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal F ϕ0 from a reference signal F ref A frequency accumulator (132, 152) is preloaded with a preload value P K1 and receives one reference signal cycle as a clock signal, receives a constant K 1 as an input thereto, with the frequency accumulator (132, 152) having a maximum count K MAX and producing an overflow output. A phase accumulator (136, 156) is preloaded with a preload value P C1 and receives one overflow cycle output from the frequency accumulator (132, 152) as a clock signal and receives a phase offset constant C 1 as an input thereto. The phase accumulator (136, 156) has a maximum count C MAX and produces a phase accumulator (136, 156) output. A delay line (320) is clocked by the reference signal F ref and produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit (140, 144; 160, 164) receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output F ϕ1 whose phase shift ϕ1 relative to F 0ϕ is a function of P K1 and P C1 .

Abstract translation: 可编程偏移时钟信号发生器具有与本发明一致的频率发生器电路（104），其从参考信号Fref A频率累加器（132,152）预加载有预加载值PK1并产生一个输出信号Fφ0，并且接收一个参考信号周期作为 时钟信号接收常数K1作为其输入，频率累加器（132,152）具有最大计数KMAX并产生溢出输出。 相位累加器（136,156）预加载有预载值PC1，并且从频率累加器（132,152）输出一个溢出周期作为时钟信号，并接收相位偏移常数C1作为其输入。 相位累加器（136,156）具有最大计数CMAX并产生输出相位累加器（136,156）。 延迟线（320）由参考信号Fref计时，并在多个抽头输出端产生多个延迟参考时钟信号。 抽头选择电路（140,144; 160,164）接收相位累加器输出，并响应于此选择抽头输出中的至少一个以产生相对于F0φ的相移φ1是PK1和PC1的函数的输出Fφ1。

公开(公告)号：WO2003052926A1

公开(公告)日：2003-06-26

申请号：PCT/US2002/039325

申请日：2002-12-10

Applicant: MOTOROLA, INC.

Inventor： STENGEL, Robert, E. ,  OLSON, Scott, A.

IPC: H03F3/60

CPC classification number: H03F3/211 ,  H03F1/3247 ,  H03F1/3294 ,  H03F3/189

Abstract: A radio frequency power amplifier circuit according to certain embodiments of the present invention uses a distributed radio frequency amplifier (110) having a plurality of stages each with an input. The distributed radio frequency amplifier (110) drives an output load, such as an antenna (114). A drive signal synthesizer (106), having a plurality of outputs, drives the plurality of inputs to the distributed amplifier (110). Changes in load impedance are measured, e.g., using a directional coupler (160), and the measurement is used to change a drive signal produced by the drive signal synthesizer (106) to compensate for the change in load impedance.

Abstract translation: 根据本发明的某些实施例的射频功率放大器电路使用具有多个级的分布式射频放大器（110），每个级具有输入。 分布式射频放大器（110）驱动诸如天线（114）的输出负载。 具有多个输出的驱动信号合成器（106）将多个输入驱动到分布式放大器（110）。 测量负载阻抗的变化，例如使用定向耦合器（160），并且测量用于改变由驱动信号合成器（106）产生的驱动信号，以补偿负载阻抗的变化。

公开(公告)号：WO2003041276A2

公开(公告)日：2003-05-15

申请号：PCT/US2002/033935

申请日：2002-10-23

Applicant: MOTOROLA, INC.

Inventor： JUAN, Jui-Kuo ,  STENGEL, Robert, E. ,  MARTIN, Frederick, L. ,  BOCKELMAN, David, E.

IPC: H03L

CPC classification number: H03L7/16 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/14 ,  H03L2207/08

Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.

Abstract translation: 在几个实施例中，延迟锁定环频率合成器使用主延迟线元件（24）和一个或多个辅助延迟元件（162 164,270,310）。 在一个实施例中，主延迟线（24）用于粗略地选择频率输出，而使用无源或有源的辅助延迟元件（162 164,270,310）来增加主延迟线的分辨率 24）。 在被动实施例中，通过从主延迟线（24）的输出抽头中选择分量作为被动次级延迟元件（310）的驱动信号来提供粗调和选择输出，可以进行粗略和精细的频率选择 从第二延迟元件（310）提供精细选择。