公开(公告)号：WO1997042662A1

公开(公告)日：1997-11-13

申请号：PCT/US1997007322

申请日：1997-04-30

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  CORNETT, Kenneth, D. ,  RAMAKRISHNAN, E., S. ,  SHAPIRO, Gary, H. ,  HOWNG, Wei-Yean

IPC: H01L29/12

CPC classification number: H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrable circuit inductor (220) is formed from a patterned conductive material (110) that has a major portion completely encapsulated by a material (221, 223) that is substantially electrically non-conductive, and that has a magnetic response at the operating frequency of the inductor (220). Preferably, an amorphous ferrite material is used for encapsulation, which provides a closed magnetic flux path for the inductor (220) when processing a signal at its operating frequency.

Abstract translation: 可集成电路电感器（220）由图案化的导电材料（110）形成，该导电材料具有完全由基本上不导电的材料（221,223）封装的主要部分，并且在工作频率处具有磁响应 的电感器（220）。 优选地，非晶铁氧体材料用于封装，当在其工作频率处理信号时，其提供用于电感器（220）的闭合磁通路径。

公开(公告)号：EP0562101B1

公开(公告)日：2000-05-03

申请号：EP92922713.0

申请日：1992-10-15

Applicant: MOTOROLA, INC.

Inventor： RAMAKRISHNAN, E., S. ,  CORNETT, Kenneth, D. ,  HOWNG, Wei-Yean

IPC: H01L45/00 ,  H01L29/92 ,  H01L27/12 ,  H03B5/12 ,  H03B5/24 ,  H03B5/36

CPC classification number: H01L29/94

公开(公告)号：EP0608376B1

公开(公告)日：2002-08-21

申请号：EP92923202.3

申请日：1992-10-15

Applicant: MOTOROLA, INC.

Inventor： CORNETT, Kenneth, D. ,  RAMAKRISHNAN, E., S. ,  SHAPIRO, Gary, H. ,  CALDWELL, Raymond, M. ,  HOWNG, Wei-Yean

IPC: H01G7/00

CPC classification number: H01L29/66181 ,  H01L29/94

Abstract: A voltage variable capacitor (10) has as the base substrate a silicon wafer with a layer of high resistivity semiconductor material on top of the substrate. An insulating layer (16) of a metal oxide having a dielectric constant greater than the dielectric constant of the semiconductors (12), such as zirconium titanate, is formed on top of the high resistivity layer, and a metal electrode (18) is formed on the insulating layer (16). When the electrode is energized, a depletion layer (20) is formed in the high resistivity layer. By varying the voltage applied to the electrode, the capacitance of the device is altered.

公开(公告)号：EP1415347A2

公开(公告)日：2004-05-06

申请号：EP02749528.2

申请日：2002-05-08

Applicant: MOTOROLA, INC.

Inventor： HIGGINS, Robert, J. ,  CORNETT, Kenneth, D.

IPC: H01L27/20 ,  H01L41/22 ,  H03H9/30 ,  H03H9/46

CPC classification number: H03H9/0542 ,  H01L27/20 ,  H01L41/314 ,  H01L41/319 ,  H03H9/02976

Abstract: An epitaxial layer of crystalline piezoelectric material such as lithium niobate and lithium tantalate can be grown overlying a silicon wafer by first growing an intermediate strain-relief layer on the silicon wafer. Early in the growth of the piezoelectric layer, the strain-relief layer is a crystalline metal oxide, which helps bridge the lattice mismatch between silicon and the piezoelectric material. After growth of a thin crystalline piezoelectric layer, the strain-relief layer is amorphized to decouple the silicon and piezoelectric crystal lattices. Growth of the piezoelectric layer may then be resumed to obtain a good quality thicker layer suitable for electro-acoustic device fabrication. Passive and active electro-acoustic devices may be fabricated using the epitaxial piezoelectric layer. In particular, acoustic charge transport devices that utilize device elements in both silicon and the piezoelectric epitaxial overlayer are designed and fabricated. The electro-acoustic devices may be integrated with semiconductor device circuitry fabricated on the silicon wafer.

公开(公告)号：WO2002081365A2

公开(公告)日：2002-10-17

申请号：PCT/US2002/010370

申请日：2002-04-02

Applicant: MOTOROLA, INC.

Inventor： CORNETT, Kenneth, D. ,  NIU, Feng

IPC: B81C

CPC classification number: H03H3/0072 ,  H03H3/007 ,  H03H9/0023

Abstract: A first type of MEMS resonator adapted to be fabricated on a SOI wafer is provided. A second type of MEMS resonator that is fabricated using deep trench etching and occupies a small area of a semiconductor chip is taught. Overtone versions of the resonators that provide for differential input and output signal coupling are described. In particular resonators suited for differential coupling that are physically symmetric as judged from center points, and support anti-symmetric vibration modes are provided. Such resonators are robust against signal noise caused by jarring. The MEMS resonators taught by the present invention are suitable for replacing crystal oscillators, and allowing oscillators to be integrated on a semiconductor chip. An oscillator using the MEMS resonator is also provided.

Abstract translation: 提供了适于制造在SOI晶片（200）上的第一类型的MEMS谐振器（1400）。 教导了使用深沟槽蚀刻制造并占据半导体芯片的小面积的第二类型的MEMS谐振器。 描述了提供差分输入和输出信号耦合的谐振器的Overtone版本。 特别地，适用于从中心点判断为物理对称的差动耦合的谐振器，并且支持反对称振动模式。 这种谐振器对于由振动引起的信号噪声是鲁棒的。 由本发明教导的MEMS谐振器适用于替代晶体振荡器，并且允许将振荡器集成在半导体芯片上。 还提供了使用MEMS谐振器的振荡器。

公开(公告)号：WO1993008578A1

公开(公告)日：1993-04-29

申请号：PCT/US1992008781

申请日：1992-10-15

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  CORNETT, Kenneth, D. ,  RAMAKRISHNAN, E., S. ,  SHAPIRO, Gary, H. ,  CALDWELL, Raymond, M. ,  HOWNG, Wei-Yean

IPC: H01G07/00

CPC classification number: H01L29/66181 ,  H01L29/94

Abstract: A voltage variable capacitor (10) has as the base substrate a silicon wafer with a layer of high resistivity semiconductor material on top of the substrate. An insulating layer (16) of a metal oxide having a dielectric constant greater than the dielectric constant of the semiconductors (12), such as zirconium titanate, is formed on top of the high resistivity layer, and a metal electrode (18) is formed on the insulating layer (16). When the electrode is energized, a depletion layer (20) is formed in the high resistivity layer. By varying the voltage applied to the electrode, the capacitance of the device is altered.

公开(公告)号：WO2003012874A2

公开(公告)日：2003-02-13

申请号：PCT/US2002/014739

申请日：2002-05-08

Applicant: MOTOROLA, INC.

Inventor： HIGGINS, Robert, J. ,  CORNETT, Kenneth, D.

IPC: H01L27/20

CPC classification number: H03H9/0542 ,  H01L27/20 ,  H01L41/314 ,  H01L41/319 ,  H03H9/02976

Abstract: An epitaxial layer of crystalline piezoelectric material such as lithium niobate and lithium tantalate can be grown overlying a silicon wafer by first growing an intermediate strain-relief layer on the silicon wafer. Early in the growth of the piezoelectric layer, the strain-relief layer is a crystalline metal oxide, which helps bridge the lattice mismatch between silicon and the piezoelectric material. After growth of a thin crystalline piezoelectric layer, the strain-relief layer is amorphized to decouple the silicon and piezoelectric crystal lattices. Growth of the piezoelectric layer may then be resumed to obtain a good quality thicker layer suitable for electro-acoustic device fabrication. Passive and active electro-acoustic devices may be fabricated using the epitaxial piezoelectric layer. In particular, acoustic charge transport devices that utilize device elements in both silicon and the piezoelectric epitaxial overlayer are designed and fabricated. The electro-acoustic devices may be integrated with semiconductor device circuitry fabricated on the silicon wafer.

Abstract translation: 通过首先在硅晶片上生长中间应变消除层，可以将晶体压电材料的外延层如铌酸锂和钽酸锂生长在硅晶片上。 在压电层的生长早期，应变消除层是结晶金属氧化物，有助于桥接硅与压电材料之间的晶格失配。 在薄晶体压电层生长之后，应变消除层非晶化以使硅和压电晶格分离。 然后可以恢复压电层的生长以获得适合于电声器件制造的优质较厚层。 可以使用外延压电层制造被动和主动的电声装置。 特别地，设计并制造了利用硅中的器件元件和压电外延覆层的声电荷传输器件。 电声器件可以与制造在硅晶片上的半导体器件电路集成。

公开(公告)号：WO1993008610A1

公开(公告)日：1993-04-29

申请号：PCT/US1992008809

申请日：1992-10-15

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  RAMAKRISHNAN, E., S. ,  CORNETT, Kenneth, D. ,  HOWNG, Wei-Yean

IPC: H01L45/00

CPC classification number: H01L29/94

Abstract: A semiconductor device (10), comprising a semiconductor substrate (12) having a layer of semiconductor material (14) deposited, coated or grown epitaxially as a single crystal or polysilicon on the surface of the substrate. The layer of material is also a semiconductor material, having a higher resistivity than the substrate it is deposited on. A dielectric layer (16) of a metal oxide is formed on the high resistivity layer (14), which is then covered with an amorphous layer (18) of a metal oxide dielectric. Zirconium titanate may be used as a metal oxide dielectric layer. A metal electrode (20) is formed on the amorphous layer (18) to form a Metal Insulator Semiconductor device. In an alternative configuration, the amorphous layer (18) may instead be placed between the high resistivity layer (14) and the dielectric layer (16), or a second amorphous layer (22) may be added between the high resistivity layer and the dielectric layer. When the device is electrically energized, a depletion region is formed in the high resistivity layer, creating a voltage variable capacitor.

公开(公告)号：EP0608376A1

公开(公告)日：1994-08-03

申请号：EP92923202.0

申请日：1992-10-15

Applicant: MOTOROLA, INC.

Inventor： CORNETT, Kenneth, D. ,  RAMAKRISHNAN, E., S. ,  SHAPIRO, Gary, H. ,  CALDWELL, Raymond, M. ,  HOWNG, Wei-Yean

IPC: H01G7 ,  H01L21 ,  H01L27 ,  H01L29

CPC classification number: H01L29/66181 ,  H01L29/94

Abstract: Un condensateur à capacité variable (10) comprend, comme substrat de base, une tranche de silicium sur laquelle est appliquée une couche d'un matériau semi-conducteur à résistivité élevée. Une couche isolante (16) composée d'un oxyde métallique présentant une constante diélectrique supérieure à celle des semi-conducteurs (12), tel que le titanate de zirconium, est formée au-dessus de la couche à résistivité élevée, et une électrode métallique (18) est appliquée sur la couche isolante (16). Lorsque l'électrode est excitée, une zone de déplétion (20) est produite dans la couche à résistivité élevée. On modifie la capacitance du dispositif en variant la tension appliquée à l'électrode.

公开(公告)号：EP0562101A1

公开(公告)日：1993-09-29

申请号：EP92922713.0

申请日：1992-10-15

Applicant: MOTOROLA, INC.

Inventor： RAMAKRISHNAN, E., S. ,  CORNETT, Kenneth, D. ,  HOWNG, Wei-Yean

IPC: H01L27 ,  H01L21 ,  H01L29

CPC classification number: H01L29/94

Abstract: Dispositif à semiconducteur (10) comprenant un substrat à semiconducteur (12) sur lequel une couche de matière semiconductrice (14) est déposée, appliquée sous forme de revêtement ou développée épitaxialement sous la forme d'un monocristal ou de polysilicium sur la surface du substrat. La couche de matière est également un matériau semiconducteur ayant une résistivité plus élevée que le substrat sur lequel il est déposé. Une couche diélectrique (16) d'un oxyde métallique est formée sur la couche de haute résistivité (14) qui est ensuite recouverte d'une couche amorphe (18) d'un diélectrique d'oxyde métallique. Du titanate de zirconium peut être utilisé comme couche diélectrique d'oxyde métallique. Une électrode métallique (20) est formée sur la couche amorphe (18) afin d'obtenir un dispositif semiconducteur isolateur métallique. Dans une variante, la couche amorphe (18) peut être placée entre la couche de haute résistivité (14) et la couche diélectrique (16), ou bien une seconde couche amorphe (22) peut être ajoutée entre la couche de haute résistivité et la couche diélectrique. Lorsque le dispositif est excité électriquement, une région d'appauvrissement se forme dans la couche de haute résistivité, créant ainsi un condensateur à tension variable.