公开(公告)号：EP2073476A3

公开(公告)日：2014-06-25

申请号：EP08172171.4

申请日：2008-12-18

Applicant: MediaTek Inc.

Inventor： Pedersen, Carsten Aagaard ,  Shen, John Zijun ,  Yan, Aiguo ,  Mathew, Deepak ,  Kocic, Marko ,  Fisher-Jeffes, Timothy Perrin ,  Keller, Thomas

IPC: H04L27/34 ,  H04L27/38

CPC classification number: H04L27/34 ,  H04L27/3809

Abstract: A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.

公开(公告)号：EP2081298A2

公开(公告)日：2009-07-22

申请号：EP08171814.0

申请日：2008-12-16

Applicant: MediaTek Inc.

Inventor： Pedersen, Carsten Aagaard ,  Shen, John Zijun ,  Yan, Aiguo ,  Mathew, Deepak ,  Kocic, Marko ,  Fisher-Jeffes, Timothy Perrin ,  Keller, Thomas ,  Aardoom, Eric ,  Ivory, David Stephen ,  Krivacek, Paul D.

IPC: H04B1/06 ,  H04L25/06 ,  G06F15/78 ,  H03M13/00

CPC classification number: G06F15/7842 ,  H04L1/0045 ,  H04L1/0052 ,  H04L1/1829

Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.

Abstract translation: 一种用于在无线系统中处理信号的装置包括：第一存储器模块，用于从一组物理信道接收输入数据;第一多个子模块，用于处理输入数据。 选择第一组多个子模块中的每一个以基于数据和传输信道规范起作用。 该设备还包括第二存储器模块以接收经处理的输入数据并输出中间数据。 第二个存储器中输入数据的位置根据数据和传输通道规格进行分配。 该装置还包括用于处理中间数据的第二多个子模块。 选择第二多个子模块中的每一个以基于数据和传输信道规范起作用。 该设备还包括第三存储器模块以接收和输出比特率处理输出。

公开(公告)号：EP2073397A1

公开(公告)日：2009-06-24

申请号：EP08171811.6

申请日：2008-12-16

Applicant: MediaTek Inc.

Inventor： Shen, John Zijun ,  Pedersen, Carsten Aagaard ,  Mathew, Deepak ,  Krivacek, Paul D. ,  Yan, Aiguo ,  Fisher-Jeffes, Timothy Perrin

IPC: H04B1/707

CPC classification number: H04B1/71055 ,  H04B1/7105 ,  H04B2201/70711 ,  H04J13/0077

Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.

Abstract translation: 一种方法包括在第一数据处理模块中接收数据，以及当接收到的数据的至少一个信号时隙包括符合第一数据传输标准的数据时启用第二数据处理模块。 该方法还包括在第一数据处理模块和在处理器中执行的软件之间交换信号，以及确定第二数据处理模块的软件配置已经完成。 该方法还包括处理第二数据处理模块中的数据用于至少一个信号时隙，以及在完成对第二数据处理模块中的至少一个数据块的处理完成时启用第三数据处理模块，并且确定 第三数据处理模块的软件配置已经完成，所述至少一个数据块包括多个信号时隙。

公开(公告)号：EP2073396A2

公开(公告)日：2009-06-24

申请号：EP08169998.5

申请日：2008-11-26

Applicant: Mediatek Inc.

Inventor： Mestechkin, Russ ,  Mathew, Deepak ,  Wang, Justin ,  Nandipaku, Sanjay

IPC: H04B1/707

CPC classification number: H04B1/707 ,  H04B2201/70707

Abstract: A wireless system has an uplink chip rate processing architecture in which at least two groups of registers are provided, each group of register storing a set of time slot configuration parameters. A storage stores a sequence of time slot configuration set identifiers each identifying one of the groups of registers, each identifier corresponding to a time slot. A chip rate processing unit processes a stream of data over a plurality of time slots in which at each of the time slots, and the chip rate processing unit is configured according to the set oftime slot configuration parameters stored in the group of register associated with the time slot configuration set identifier corresponding to the time slot.

Abstract translation: 无线系统具有其中提供至少两组寄存器的上行链路码片速率处理架构，每组寄存器存储一组时隙配置参数。 存储器存储一系列时隙配置集标识符，每个识别寄存器组中的一个，每个标识符对应于时隙。 芯片速率处理单元在多个时隙中处理数据流，其中在每个时隙处，并且芯片速率处理单元根据存储在与所述时隙相关联的寄存器组中的时隙配置参数的集合来配置 与时隙对应的时隙配置集标识符。