公开(公告)号：US20240155823A1

公开(公告)日：2024-05-09

申请号：US18411046

申请日：2024-01-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI ,  Chun-Heng WU

IPC: H10B12/00 ,  H01L29/92

CPC classification number: H10B12/00 ,  H01L28/40 ,  H01L28/92 ,  H01L29/92

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

公开(公告)号：US20220344340A1

公开(公告)日：2022-10-27

申请号：US17241370

申请日：2021-04-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Li-Han LIN ,  Jen-I LAI ,  Chun-Heng WU

IPC: H01L27/108

Abstract: The present disclosure provides a semiconductor structure having a memory structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a trench capacitor. The trench capacitor is disposed in a trench penetrating the first layer, the second layer, and the third layer. The trench capacitor includes a bottom metal layer, a middle insulating layer, and a top metal layer. The bottom metal layer covers a side wall of the first layer, a side wall of the second layer, and a first portion of a side wall of the third layer. The middle insulating layer covers the bottom metal layer and a second portion of the side wall of the third layer. The top metal layer covers the middle insulating layer.

公开(公告)号：US20210090957A1

公开(公告)日：2021-03-25

申请号：US17099234

申请日：2020-11-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chun-Heng WU

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates to a FinFET structure and a method of manufacturing the same. The FinFET structure includes a first fin and a second fin. The first fin is over a first base and has a first channel region. The first channel region has a first channel length. The second fin is over a second base and has a second channel region. The second channel region has a second channel length. The second channel length is different from the first channel length.