公开(公告)号：US20220093402A1

公开(公告)日：2022-03-24

申请号：US17029023

申请日：2020-09-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI ,  Chun-Heng WU ,  Rou-Wei WANG

IPC: H01L21/28 ,  H01L21/033 ,  H01L29/40

Abstract: A method of manufacturing a semiconductor device is provided. A precursor structure is formed, in which the precursor structure includes a patterned substrate having at least one trench therein, an oxide layer covering the patterned substrate, and a nitride layer on the oxide layer and exposing a portion of the oxide layer in the trench. A first barrier layer and a first gate structure is formed on the oxide layer. A portion of the first barrier layer is removed with an etchant including CF4, C2F6, C3F8, C4F8, F2, NF3, SF6, CHF3, HF, COF2, ClF3 or H2O2 to expose a sidewall of the oxide layer. A second barrier layer is formed on the first gate structure and the oxide layer. A portion of the second barrier layer is removed with the etchant. A second gate structure is formed on the second barrier layer.

公开(公告)号：US20220069070A1

公开(公告)日：2022-03-03

申请号：US17010843

申请日：2020-09-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI ,  Chun-Heng WU

IPC: H01L49/02

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternatively stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

公开(公告)号：US20240049439A1

公开(公告)日：2024-02-08

申请号：US17818007

申请日：2022-08-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chia Che CHIANG ,  Jen-I LAI ,  Chun-Heng WU

IPC: H01L27/108

CPC classification number: H01L27/10852

Abstract: A method of forming semiconductor structure includes forming a dielectric stack over a substrate. A mask layer is formed over the dielectric stack. A first opening is formed in the mask layer to expose dielectric stack. A second opening is formed in the dielectric stack to expose the substrate, wherein the second opening is communicated with the first opening. A fill layer is formed in the first opening and the second opening. The mask layer and the fill layer are removed such that sidewalls of the dielectric stack are exposed. A capacitor is formed in the second opening of the dielectric stack.

公开(公告)号：US20220102347A1

公开(公告)日：2022-03-31

申请号：US17643411

申请日：2021-12-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI ,  Chun-Heng WU

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/92

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

公开(公告)号：US20240347461A1

公开(公告)日：2024-10-17

申请号：US18755686

申请日：2024-06-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chun-Wei WANG ,  Jen-I LAI ,  Rou-Wei WANG

IPC: H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226

Abstract: A method of manufacturing a semiconductor structure includes a number of operations. A first oxide layer is provided on a semiconductor integrated circuit. A conductive layer of the semiconductor integrated circuit is exposed from a top surface of the first oxide layer. An etch stop layer is formed on the top surface of the first oxide layer. A second oxide layer is formed on the etch stop layer. A through via is formed extending through the second oxide layer and the etch stop layer to expose the conductive layer. Acid is provided on the conductive layer to form a protective layer on the conductive layer. The protective layer includes a compound of the acid and material of the conductive layer. A fence of the second oxide layer at an edge on the through via is removed at the through via by a hydrofluoric acid etching.

公开(公告)号：US20220351961A1

公开(公告)日：2022-11-03

申请号：US17243159

申请日：2021-04-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Rou-Wei WANG ,  Jen-I LAI ,  Chun-Heng WU ,  Jr-Chiuan WANG ,  Chia-Che CHIANG

IPC: H01L21/02 ,  H01L21/762

Abstract: The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C2F6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

公开(公告)号：US20220020752A1

公开(公告)日：2022-01-20

申请号：US16933976

申请日：2020-07-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI ,  Chun-Heng WU

IPC: H01L27/108 ,  H01L21/311

Abstract: A method for manufacturing a capacitor includes: providing a substrate and a multilayer structure; forming a recess in the multilayer structure; forming a first electrode layer on a surface of the recess; performing a selective etching treatment to remove the first and second stack material layers; performing a selective vapor phase etching treatment to the first electrode layer to form a smaller thickness of the first electrode layer; and forming a dielectric layer and a second electrode layer in which the dielectric layer is between the first and second electrode layer.

公开(公告)号：US20240413005A1

公开(公告)日：2024-12-12

申请号：US18208142

申请日：2023-06-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: providing a semiconductor structure, in which the semiconductor structure comprises a silicon substrate having a plurality of trenches and an oxide material filled in the trenches and covering the silicon substrate, and the trenches define a plurality of island structures; forming a pad oxide layer on a top portion of the oxide material, in which the pad oxide layer is located over the silicon substrate; and removing the pad oxide layer, so that a top surface of the oxide material and a top surface of the island structures are coplanar.

公开(公告)号：US20240172414A1

公开(公告)日：2024-05-23

申请号：US18056724

申请日：2022-11-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI

IPC: H01L21/02

CPC classification number: H01L27/10805 ,  H01L27/10885

Abstract: A semiconductor structure includes a substrate, a bit line structure, an oxide barrier layer, and a bit line capping layer. The bit line structure is disposed on the substrate, in which the bit line structure includes a conductive silicon layer, a conductive layer, and a hard mask layer. The conductive layer is disposed on the conductive silicon layer, in which the conductive layer includes a metal. The hard mask layer is disposed on the conductive layer. The oxide barrier layer is disposed in direct contact with a sidewall of the bit line structure. The bit line capping layer covers the oxide barrier layer.

公开(公告)号：US20240155823A1

公开(公告)日：2024-05-09

申请号：US18411046

申请日：2024-01-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jen-I LAI ,  Chun-Heng WU

IPC: H10B12/00 ,  H01L29/92

CPC classification number: H10B12/00 ,  H01L28/40 ,  H01L28/92 ,  H01L29/92

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.